Conclusions; Based on the very popular RGC circuits and the inherent bi-directional property of MOS transistors, a new CMOS four-quadrant multiplier is introduced. This multiplier, using only two MOS transistors, operated in the triode region with RGC structures to realise four-quadrant multiplication. Simulation results have been given to demonstrate its feasibility. This multiplier has a simple configuration and is expected to he suitable for low voltage applications. ”OD 0 IEE 1995 8 March 1995 Electronics Letters Online No: 19950638 Jiann-Horng Tsay, Shen-Iuan Liu, Jiann-Jong Chen and Yan-Pei Wu (Department of Electrical Engineerinx, National Taiwan Unii’ersirj, Taipei, Taiwan 10664, Republic of China) References m vss Fig. 3 C M O S implementation ofproposed,four-quadrant multiplier 1 Circuit implementation and simulation results: The complete circuit diagram of the proposed multiplier is shown in Fig. 3, where M9 M18 form the three differential amplifiers in Fig. 2 according to [3] and the output current I,, is converted to an output voltage V,, through the connection of two 1 kC2 load resistors. This circuit has been simulated using PSpice with a level I1 model of a standard 2 p n CMOS process. The width-to-length ratios of all transistors used in the simulation are listed in Table 1 . All simulations were performed with supply voltages of f 3 V V, = OV, and with all nMOS transistors sharing the same bulk, connected to Vyp Fig. 4 shows the DC transfer curves for this multiplier. Similar curves were obtained by interchanging V,-V, and V,-V4. This circuit has < 1 % nonlinearity error over a + l A V differential input range. For a l0kHz differential input signal having a 1.XV peak amplitude applied to Vi and V, (common mode level set to 2.1 V), with V,- V4 held constant at l.XV, the output voltage had a THD of 0.064%. When the same signal was applied to V, and V, (common mode level set to -1.3V), the output voltage had a T H D of 0.60%. The simulated -3dB bandwidth was about I7MHz. Note that the input range of V3 and V, in Fig. 3 is limited to VTo < min( V,, V,) and max(V,, V,) < min(V,, V,) - V, for proper operation, where Vro is the threshold voltage of M6 (M9) and V , is the threshoid voltage of MI (M2). However, at the expense of additional power dissipation and circuit complexity, this limitation can be relaxed by inserting level shifiers, as adopted in [5, 61, to reduce the lower limit on the input range of V, and V,. 2 3 4 5 6 7 8 S A C K I N G E R .E., and GUGGENBUHL. w.: ‘A high-swing, high impedance MOS cascade circuit‘, IEEE J. Solid-Stute Circuits, 1990, 25, pp. 289-298 GATTI. u., MALOBERTI, F , and TORELLI. G.: ‘A novel CMOS linear transconductance cell for continuous-time filters’. Proc. IEEE Int. Symp. on Circuits and Systems, 1990, pp. 1173-1176 ABEL. C , SAKURAI, S , LARSEN. F., and ISMAIL. M.: ‘Four-quadrant CMOSiBiCMOS multipliers using linear-region MOS transistors’. Proc. IEEE Int. Symp. on Circuits and Systems, 1994, pp. 273-276 WYSLNSKI, A.: ‘Low-voltage CMOS and BiCMOS triode transconductors and integrators with gain-enhanced linearity and output impedance’, Electron. Left., 1994,30, pp. 21 1-213 LEE.SO, PARK,S.B, and L E E , K . R : ‘New CMOS triode transconductor’, Electron. Lett., 1994, 30, pp. 946-948 conm, A L , and ALLEN, P.E.: ‘Low-voltage, four-quadrant, analogue CMOS multiplier’, Electron. Lett.. 1994, 30,pp. 1044-1045 COBAN. A.L., and ALLEN, P.E.: ‘Low-voltage CMOS transconductance cell based on parallel operation of triode and saturation transconductors’, Electron. Lett., 1994, 30, pp. 11241 I26 LIU. s I: ‘Low voltage CMOS four-quadrant multiplier’, Electron. Lett.. 1994, 30, pp. 2125-2126 Two-stage neural network scheme for postfabrication circuit tuning P.C.K. Liu and V.W.W. Chung Table 1: Width-to-length ratios of transistors in Fig. 3 used for simulations Transistors 1 MI-M2 1 M3-M5 I MGM10 /Mll-MI51MBl-MB3 wmiiumi I io/so I 10015 I ioiio I 5015 > 0- >o -20- -40~ -2 , , , , 0 1 “1-Vz.V , , 2 1 mz Fig. 4 Simulated D C transfer curves for proposed multiplier ELECTRONICS LETTERS A two-stage system of simple identical neural networks for postfabrication tuning of electronic circuits is proposed. The first stage selects the tuning parameters and the second stage estimates the corresponding tuning level of each tuning parameter. Convergence and accuracy are shown to be superior to those of a single stage of similar complexity. I ioiio 20- ; Inde.Yina terms: lnreararrd circuits. Tuninp 8th June 1995 Vol. 31 Introduction: In electronic circuit manufacturing, postfabrication tuning is often required to bring the circuit performance up to specification. Tuning can be considered as a repair process whereby one or more of the circuit parameter values is altered to improve circuit performance. A repair operator. judging from the display of the performances, has to answer two questions: which parameters should be tuned, and how much tuning is required for each. The tuning process is highly empirical and depends on the experience of the operator. The employment of expert systems and machine learning has been proposed [ I , 21. In this Letter, a neural network based computer-aided method of tuning circuits is proposed that aims to minimise dependency on the human judgment. This approach will be particularly valuable when multiple tuning parameters are involved. Experimental results show that a singlestage hackpropagation neural network suffers a long convergence period but does not produce an acceptable proportion of correct output classifications. Therefore, a two-stage network is proposed. The input to the neural networks includes a set of performance measurements such as frequency responses. The outputs from the respective neural networks are the selection of tuning parameters No. 12 963 I and the corresponding tuning levels. When the performance of a particular circuit meets specifications, the outcome will be a null parameter selection. A large set of input-output pairs are used as training samples which could be obtained empirically, analytically or by using simulation techniques. input Q stage 1 network output parameters and direction input input output positive tuning output negative tunirQ m Fig. 1 Hierarchical structure of two-stage network Two-stage network: Fig. 1 shows the structure of the two-stage network. The first stage has only one network N , , whereas the second stage comprises two groups of networks, one for positive tuning and the other for negative tuning. The output from stage 1 points to a particular network on stage 2 for level prediction. This hierarchical system of networks consists of (n,, + n, + 1) simple and identical backpropagation neural networks where n,, and n,, are the number of tunable parameters in the positive and negative directions, respectively. A tunable parameter which can be tuned both ways requires one network in the positive direction and one in the negative direction. A laser-trimmed microwave stripline, for example, allows only negative tuning. In our work, we have assumed that all the parameters are tunable in both directions so that np = n,,. The neural networks in our experiments have identical [input10-20-output] structures of which only two layers are hidden. There is no obvious advantage in using a more complex network. Correct classification of neural network output: The inputs to the networks are features, such as the frequency response, of the circuit while the outputs are the possible tuning parameters and the corresponding tuning levels of each parameter, as discussed previously. The frequency responses are preprocessed and weighted to avoid illcouditioning. Circuits with symmetry properties, that is, f i x ,,...,x i,..., x,,..., x,,) = A x ,,..., x,,....x ,....,x,), where f ( x ) denotes the frequency response function, would cause confusion to the network and hence error in classification. It was proposed that at least one additional feature be included in the input to break the symmetry properties of the circuit [3]. A j t h output of a network o, can be classified as level k if it meets the following conditions: where 2r is the total tuning range, q is the number of tuning levels allowed, r, is the starting value of the tuning range and the predicted output value of o, = k. This classification method is as shown in Fig. 2. The ratio r / ( q - 1) defines the resolution of the correct output prediction. where M is the number of training samples, w,~" is the weight between thejth neuron in the (m-l)th layer and the kth neuron in the mth layer, nN is the number of output nodes at the Nth layer of the network and dk, is the difference between the actual and desired kth output of the ith training. The two values, M;," and b,", are updated according to the learning rate, the jtb output of the (m-l)th layer and their changes along the negative gradient of error caused by the ith sample. It is these two values that characterise the neural network with properties shaped by the training samples. Examples and results: The first example is a simple three component lowpass filter. Two of the three components are symmetrical to each other. Results for the two-stage neural network are compared to those of a single-stage neural network in Table 1. Note that the value of the error function for the two methods are for reference only since the number of terms summed in the two cases are different. Table 1: Results of lowpass filter example Method Proportion of correct output classification Value of error function Parameter 1 Parameter 2 Parameter 3 I h 12.4 Single-stage I I Single-stare I I '% 64.7 23.4 85.1 (stage I ) Two-stage Method Y" 13.8 88.85 90.75 0.222 (stage 2) Proportion of correct output classification Value of error II Parameter 2 Parameter I function Two-stage 0% 72.1 I 92.2 h 68.3 90.4 I I 71.81 594.86 (stage I ) 1.58 (stare 2) I Conclusion: In this Letter, a two-stage hierarchical neural network architecture is proposed for solving the functional postfabrication tuning problem. Results from the two examples show that this approach can achieve a much higher percentage of correct classification in terms of tuning parameter selection and prediction of tuning levels than a single stage. Further work is required to improve the proportion of correct output classification and to simplify the architecture by combining the positive and negative directions. 0 IEE 1995 Electronics Letters Online No: 19950658 9 May 1995 P.C.K. Liu and V.W.W. Chung (Department of Electronic Engineering, The Hong Kong Polytechnic University, Hung Horn, Kowloon, Hong Ref erences tuning parameter value R, R, + 2r Fig. 2 Mapping of neural network output to tuning level The stopping criteria depends on an error function which is a measure of how well the neural network describes the relationship between the input and output domain characterised by the training samples. Such an error function, E in eqn. 2, is to be minimised by the backpropagation learning rule. 964 r - MIRZAI, A.R., JERVIS, B.w., and COWAN. c F.N.: 'Comparison of knowledge elicitation technique in the domain of electronic filter tuning', IEE Proc., 1990, 137, (3, pp. 337-344 2 MIRZAI, A.R., COWAN, c.F.N., and CRAWFORD, T.w.: 'Intelligent alignment of waveguide filters using machine learning approach', IEEE Trans., 1989, MTT-37, (l), pp. 166173 3 CHUNG. v.w.w., LIU. Pc.K., and LI, K.c.: 'Solving functional postfabrication tuning of circuits with symmetry problems by introducing an additional feature to neural network learning', Electron. Lett., 1995, 31, pp. 27-29 I TSAFTINOS, D , ELECTRONICS LE7TERS 8th June 1995 ~~ Vol. 31 No. 12

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