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pttsa otchet lr2 (2)

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?????? ??3-61
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??????, 2012
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???????? ????? ????? Verilog. ???????? ???????? ????????????? ???????? ???? ? ?????? ModelSim.
1. ???????
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module cntr ( input clk, enable, reset, output reg [3:0] count );
always @ (posedge clk or negedge reset) begin
if (!reset) count <= 0; else if ((enable == 1'b1)&&(count!=5)) count <= count + 1;
end endmodule
???????? ????????
`timescale 1ns/1ps module counter_test; integer i; reg clk,ena,rst; wire [3:0] result; initial begin clk=0; forever #10 clk = ~clk; end initial begin ena=0; forever @(negedge clk) ena= ~ena;
end initial begin rst=0; #10 rst=1; while (result<5) #20 $strobe("Counter value: %d", result); #100 rst=0; #10 rst=1; #100 $stop; end bin_cnt test_dev(clk, ena, rst, result); endmodule
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2. ??????????
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module decode_shift #(parameter WIDTH = 3)
(input [WIDTH-1:0] din, output reg [2**WIDTH-1:0] dout); always @(*) dout=1<<din;
endmodule
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`timescale 1ns/1ps
module decode_test; localparam WIDTH = 4; reg [WIDTH-1:0] enc_data; wire [2**WIDTH-1:0] dec_data; initial
begin
enc_data=0; repeat (2**WIDTH) begin
$strobe("Input value: %d; output value: %b; time: %d", enc_data,dec_data,$time);
#10 enc_data=enc_data+1; end
$stop; end
decode_shift #(WIDTH) test_dev(enc_data,dec_data); endmodule
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3. ????????????? ???????
??????
module project
#(parameter width = 9)
( input clk, reset,
input [width-1:0] limit,
output reg [width-1:0] count ); //assign limit = width-1;
reg flag=1;
always @ (posedge clk or negedge reset)
begin
if(!reset)
begin
count<=0;
flag<=1;
end else
begin
if(flag==0) count=count-1;
if (count==limit)
flag<=0; else
begin if (flag==1) count<=count+1; if (count==0)
flag=1;
end
end
end endmodule
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`timescale 1ns/1ps
module test;
localparam width=9; reg clk,rst;
wire [width-1:0] result;
wire [width-1:0] limit;
assign limit=15;
initial begin
clk=0;
forever #10 clk = ~clk;
end
initial
begin
rst=0;
#11 rst=1;
#1001 $stop;
end
project test_dev(clk,rst,limit,result);
endmodule
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4. ????????????? ? ?????????????? ????????
???????
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vsim work.cntr
add wave -noupdate -format Logic /cntr/clk
add wave -noupdate -format Logic /cntr/enable
add wave -noupdate -format Logic /cntr/reset
add wave -noupdate -format Literal -max 5.0 -radix decimal /cntr/count
force reset 0 0ns, 1 20ns,0 240ns, 1 260ns
force clk 0 0ns, 1 10ns -r 20ns
force enable 0 0ns, 1 20ns -r 40ns
run @340ns
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