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Патент USA US3422290

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Jan. 14, 1969
o. E. MURRAY ETAL'
_ 3,422,283
NORMAL AND ASSOCIATIVE READ OUT CIRCUIT
FOR LOGIC MEMORY ELEMENTS
Filed July 15, 1965
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Donald E. Murray‘
BY
Walter C. See/boch
_ % 450/ M/ZM
ATT'YS.
United States Patent 0
3,422,283
Patented Jan. 14, 1969
2
1
3,422,283
NORMAL AND ASSOCIATIVE READ OUT CIRCUIT
FOR LOGIC MEMORY ELEMENTS
Donald E. Murray and Walter C. Seelbach, Scottsdale,
Ariz., assignors to Motorola, Inc., Franklin Park, Ill.,
a corporation of Illinois
switching means operative to bypass said output resistor
to change said output signal.
The invention is illustrated in the drawings in which:
FIG. 1 is a partial block diagram and partial schematic
diagram showing the read out circiut of the invention; and
FIG. 2 is a partial schematic and partial block diagram
of a modi?ed form of the circuit of FIG. 1.
In practicing this invention, a memory element is pro
vided having a binary number stored therein. The num
ber stored in the memory element operates to bias switch
This invention relates to logic gate circuits and in par 10 ing transistors to control the ?ow of current through one »
ticular to an output gating circuit for accomplishing a
of two paths with each path including the same output
“normal” read out or an “associative” read out of a mem
resistor across which an output signal is developed. By
ory circuit.
pass switching transistors are coupled in each current path
Filed July 15, 1965, Ser. No. 472,177
US. Cl. 307-207
Int. Cl. H03k 19/08
8 Claims
Logic circuit elements, employing semiconductor de
to provide a separate path for bypassing the output resistor
vices, have been developed in which the logic functions 15 to change the output signal. Separate bypass transistors
are performed by switching currents between alternative
are provided for “associative” read out and a “normal”
paths. One form of these logic elements acts as a memory
read out. A modi?ed embodiment of this circuit permits
element to store data and it is necessary that circuitry be
the “normal” read out function only to be accomplished
provided to read out the information stored in the mem
with a minimum number of components.
ory elements. Two types of read out are required, a “nor 20
FIG. 1 is a partial block diagram and a partial sche
ma ” read out and an “associative” read out. With “nor
matic diagram of a circuit incorporating the features of
mal” read out data stored in the memory is read out upon
this invention. A logic memory element 10 is provided
the application of a “read” signal. For an example, if a
which is capable of storing a “0” or “1.” The “0” output
“1” is stored in the memory, the application of the “read”
25 of logic memory element 10 is ‘coupled to base 20 of tran
signal should develop a “1” at the output of the read out
sistor 18 and the “1” output of logic memory element 10
circuit. With “associative” read out an output is developed
is coupled to base 14 of transistor 12. If a “0” is stored
from a memory if the data stored in the memory is a mis
in logic memory element 10, transistor 18 is biased to con
match with the “associative” read out signal and no output
duction and if a “l” is stored in logic memory element 10
is obtained if the data stored in the memory matches the
30 transistor 12 is biased to conduction. Resistors 8 and 9
read out signal. For example, if a “1” is stored in the
are load resistances for the output of logic ‘memory ele
memory the application of a “search ‘0’ ” signal would
ment 10. Resistor 23 couples emitters 15 and 21 of tran
produce a “1” output at the “associative” read out ter
sistors 12 and 18 to a ?rst reference potential.
minal while the application of a “search ‘1’ ” signal
By using each of the logic outputs of logic memory
would produce a “0” output at the “associative” read out
35 element 10 to control transistors 12 and 18 instead of
terminal.
coupling the base of one of the transistors to a reference
Prior art devices capable of operating at high speed
have required that more than one unit of current be
switched in order to perform the above functions. The re
quirement that more than one unit of current be switched
in each of the read out gates will cause a large increase in
power consumption of devices such as computers in which
large numbers of the read out circuits are incorporated.
Some prior art circuits have operated the semiconductor
devices in a saturated condition thus slowing the opera
tion of the circuitry. In addition, it is desirable that the
components used in the circuits be limited to transistors,
diodes and resistors so that the circiut may be easily fab
ricated in an integrated circuit form.
It is, therefore, an object of this invention to provide
‘an improved read out circuit for a logic memory element.
Another object of this invention is to provide a read
out circuit for a logic memory element capable of ‘per
potential, an improved noise immunity can be obtained
for the same logic swing or the logic swing can be reduced
without a reduction in the noise immunity. Reducing the
logic swing reduces the RC time constant of the memory
element circuit, thus increasing the speed of operation of
the memory element circuit. The reduction in logic swing
also reduces the tendency of the logic memory element
circuit to saturate with changes in power supply voltage
and ambient temperature.
’
A power supply 24 is coupled to the ?rst reference po
tential and to collectors 32 and 35 of transistors 28 and
34 by output resistor 26. Emitters 31 and 37 of transistors
28 and 34 are coupled to collectors 16 and 22 of transistors
12 and 18. A second reference voltage VBB is coupled
from terminal 33 to bases 30 and 36 of transistors 28 and
34 to provide a' bias potential for these transistors.
Emitter 41 of transistor 38 is coupled to emitter 37
forming both “normal” read out and “associative” read
of transistor 34 and collector 42 of transistor 38 is cou
out.
pled to power supply 24. Transistor 38 is adapted to
Another object of this invention is to provide a read
out circiut for a logic memory element which requires
only one unit of current for operation and in which the
semiconductor devices used in the circuit operate in an
receive a “search ‘1’ ” signal on its base 40. Emitters 47
and 53 of transistors 44 and '50 are coupled to emitter 31
of transistor 28 and collectors 48 and 54 of transistors
44 and 50 are coupled to power supply 24. Transistor 44
unsaturated condition.
60 is adapted to receive a “search ‘0’ ” signal on its base 46
Another object of this invention is to provide a read
and transistor 50 is adapted to receive a “read” signal on
out circuit having only transistors, diodes and resistors so
its base 52. “Read” output transistor 56 has its emitter
that the circuit is readily adaptable to construction as an
59 coupled to “read” output terminal 61 and load resistor
integrated circuit.
57, and its collector 60 coupled to power supply 24. A
bias signal is supplied to base 58 of transistor 56 from
output resistor 26. “Associative” output transistor'62 has
its emitter 65 coupled to the “associative” output terminal
current through different paths with each of the paths
67 and load resistor 63, and its collector 66 coupled to
including the same output resistor to develop an output
power supply 24. A bias signal is supplied to base 64 of
signal.
70 transistor 62 from resistor 26. Since a load resistor only
appears in the collector circuit of transistors having their
Another feature of this invention is the provision of a
bases connected to the reference voltage VBB some satu
read out circiut for a logic memory element having bypass
A feature of this invention is a provision of a read out
circuit for a logic memory element in which the data
stored-v within the memory element controls the ?ow of
3
3,422,283
ration margin is gained over circuits in which a load re
sistor is connected to the collector circuit of transistors
having their bases tied to logic level inputs.
In describing the operation of the circuit of FIG. 1,
4
logic memory element 10 transistor 18 is conducting and
transistor 12 is non-conducting. Current will flow through
output resistor 26, transistor 34, transistor 18 and resistor
23. Attempting to bias transistor 50 to conduction by
assume that a “0” is stored in logic memory element 10.
applying a read signal to base 52 of transistor 50 does not
The “0” signal applied to base 29‘ of transistor 18 will bias 5 change the ?ow of current through output resistor 26,
transistor 18 to conduction. In normal operation when
since transistor 50 can be biased to conduction only if
there is no “associative search” or “read” signal applied
transistor 12 is biased to conduction. Thus, the output
to the circuit the reference voltage VBB applied to terminal
'bias applied to base 58 of transistor 56 is low and the
33 biases either transistor 28 or 34 to conduction depend
potential at the “read” output terminal 61 is low. If a
ing upon whether transistor 12 or 18 respectively is biased
“1” is stored in logic memory element 10 transistor 12
to conduction. Thus, with a “0” stored in logic memory
is biased to conduction and the current flow is from power
element 10 current will flow from power supply 24 through
supply 24 through output resistor 26, transistors 28 and
output resistor 26, transistor 34, transistor 18 and resistor
12 and resistor 23. Biasing transistor 50 to conduction cuts
23 to the ?rst reference potential. The magnitude of this 15 off the ?ow of current through output resistor 26. When
current is substantially constant and is determined by the
no current flows through output resistor 26, the potential
level of the “0” signal applied to base 20 of transistor 18
applied to base '58 of transistor 56 is high and the poten
and resistor 23.
tial at the “read”output terminal 61 is high.
Current will not flow through transistor 28 since tran
A partial block diagram and partial schematic of a
sistor 12 is biased to non-conduction, thus forcing tran
circuit modi?ed to incorporate only the “read out” fea
sistor 28 to be biased to non—conduction. If a “1” is stored
ture is shown in FIG. 2. In FIG. 2, components identical
in logic memory element 10, transistor 12 will be biased
to those of FIG. 1 have the same reference numeral. Base
to conduction and transistor 18 will be biased to non-con
90 of transistor 88 is coupled to a reference potential VBB
duction. Current will then flow through output resistor 26,
applied to terminal 94. When there is no “read” signal
transistors 28 and 12 and resistor 23. In each case a single 25 applied to “read” terminal 86 the potential applied to
base 82 of transistor 80 is low. When a “1” is stored in
logic memory element 10, transistor 80 is biased to non
unit of current ?ows through output resistor 26 and the
magnitude of this current is substantially constant. The
?ow of current through output resistor 26 reduces the bias
potential applied to the bases 58 and 64 of transistors 56
conduction and transistor 88 is biased to conduction.
Under these conditions current flows from power supply
and 62 biasing each of the transistors to a minimum con
24 through output resistor 78, transistor 88, transistor 12
duction condition. Thus, the output potential on both
“read” terminal 61 and “associative” output terminal 67
is low.
and resistor 23. If a “0” is stored in logic memory element
If it is desired to conduct an “associative search,” to
determine if a “l” is stored in logic memory element 10 v
a “search ‘1’ ” signal is applied to base 40 of transistor
38. The result of the search should be a high output from
the “associative” output terminal 67 if there is a mismatch
or a “0” stored in logic memory element 10 and a low
output from the “associative” output terminal 67 if there 40
10 the ?ow of current is from power supply 24 through
output resistor 78, transistor 18 and resistor 23. In each
case, the voltage drop across resistor 78 produces a low
output potential on base 98 of transistor 96 and thus a
low output potential on “read”output terminal 102.
With “0” stored in logic memory element 10, a “read”
pulse applied to terminal 86 will attempt to bias transistor
80 to conduction. However, since transistor 12 is biased
to non-conduction current will not flow through. transistor
is a match or a “1” stored in logic memory element 10.
80 and current will continue to ?ow through output re
When a “O” is stored in memory element 10 and a
sistor 78. Thus, the potential applied to base 98 of tran
search signal is applied to the “search ‘1’ ” terminal, base
sistor 96 continues to be low and the output potential of
40 of transistor 38, transistor 38 is biased to conduction
“read” output terminal 102 is low. If a “l” is stored in
and transistor 34 is biased to non-conduction since emitters 45 logic memory element 10, transistor 12 is biased to con
37 and 41 of transistors 34‘ and 38 are coupled together.
duction and current ?ows from power supply 24 through
Thus, current now flows from power 'supply 24 through
resistor 78, transistors 88 and 12 and resistor 23. A “read”
transistor 38, transistor 18 and resistor 23. While the
signal applied to terminal 86 biases transistor 80 to con
magnitude of the current through the circuit is unchanged
duction causing the current to bypass output resistor 78
the magnitude of the current through resistor 26 is reduced 50 and ?ow through transistors 80 and 12 and resistor 23.
to zero and the potential applied to base 64 is high. This
When the ?ow of current through output resistor 78
high potential applied to base 64 biases transistor 62 to
ceases, the potential on base 98 of transistor 96 rises caus
a maximum conduction state and produces a high output
ing the potential on the “read” output terminal 102 to
signal at “associative” output 67. If a “1” were stored in
rise indicating that a “1” is stored in logic memory ele
logic memory element 10 a “search” signal applied to the 55 ment 10.
search “0” terminal would produce high output signal at
Thus, a simple circuit has been described which pro
“associative” output 67.
vides for reading out the information stored in a logic
If a search were to be conducted for a “0” a “search
memory element. The circuit is capable of both “associa
‘0”’ signal would be applied to base 46 of transistor 44
tive” read out the “normal” read out. The semiconductor
which would attempt to 'bias transistor 44 to conduction. 60 devices used operate in an unsaturated condition permit
However, since a “0” is stored in logic memory element
ting high speed operation and no more than one unit of
10, transistor 12 is biased to non-conduction thus requiring
current ?ows in the read out circuit. Only transistors and
transistor 44 to be biased to non-conduction. Current will
resistors are used in the circuit so that it is readily adapt
continue to ?ow through output resistor 26, transistor 34
able to integrated circuit construction.
and transistor 18 and the output potential applied to base 65
We claim:
64 of transistor 62 would remain low because of the volt
1. A read out gate circuit for use with a memory circuit
age drop across resistor 26. Thus, with a “0” stored in
adapted to store ?rst and second data signals one at a
logic memory element 10‘ a search for a “0” would pro
time, said read out gate circuit including in combination,
duce a low output from “associative” output terminal 67.
power supply means for providing a current, ?rst and
If a “1” were stored in logic memory element 10 a search 70 second current paths coupled to said power supply means,
signal applied to the “search ‘1’ ” terminal would produce
impedance means common to each of said ?rst and second
a low output from the “associative” output terminal 67.
current paths, said ?rst and second current paths further
If it is desired to read out the information stored in
including ?rst and second data switching means respec
logic memory element 10 a signal is applied to the “read”
tively coupled to the memory element, a given one of
terminal, base 52 of transistor 50. If a “0” is stored in 75 said ?rst and second data switching means being respon
3,422,283
6
sive to the particular one of the ?rst and second data sig
nals stored in the memory circuit to become conductive
ibecome conductive and to render said current switching
means coupled thereto non-conductive whereby a third
whereby said current flows through the current path in
cluding said given data switching means and through said
impedance means, bypass switching means coupled to
output means coupled to said impedance means and re
at least one of said current paths and adapted to receive
a read signal, said bypass switching means being respon
sive to said read signal to become conductive whereby a
third current path bypassing said impedance means is
provided, output means coupled to said impedance means
and responsive to the magnitude of said ?ow of current
through said impedance means to develop ?rst and second
output signals.
2. A read out gate circuit for use with a memory circuit
adapted to store ?rst and second data signals one at a
time, said read out gate circuit including in combination,
current path bypassing said impedance means is provided,
sponsive to the magnitude of said ?ow of current through
said impedance means to develop ?rst and second output
signals.
4. A read out gate circuit for use with a memory circuit
adapted to store ?rst and second data signals one a time,
said read out gate circuit including in combination, power
supply means for providing a current coupled to a refer
cnce potential, impedance means coupled to said power
supply means, ?rst and second current paths each coupled
to said impedance means and said reference potential, said
?rst current path having ?rst data switching means coupled
to the memory circuit for receiving the ?rst data signal
and being responsive thereto to become conductive, said
second current path having second data switching means
reference potential, impedance means coupled to said
coupled to the memory circuit for receiving the second
power supply means, ?rst and second current paths each
coupled to said impedance means and said reference 20 data signal and being responsive thereto to become con
ductive, said ?rst current path further having normally
potential, said ?rst current path having ?rst data switch
conductive current switching means coupled in series with
ing means coupled to the memory circuit for receiving
said ?rst data switching means, a given one of said ?rst
the ?rst data signal and being responsive thereto to be
and second data switching means being responsive to the
come conductive, said second current path having second
data switching means coupled to the memory circuit for 25 particular one of the ?rst and second data signals stored
in the memory circuit to become conductive whereby said
receiving the second data signal and being responsive
power supply means for providing a current coupled to a
thereto to become conductive, at least one of said ‘?rst and
current flows through the current path including said given
data switching means and through said impedance means,
bypass switching means coupled to said current switching
means and to said power supply means, said bypass
ing means included in said one current path, a given one
switching means being adapted to receive a read signal
of said ?rst and second data switching means being re
and being responsive thereto to become conductive and to
sponsive to the particular one of the ?rst and second data
render said current switching means coupled thereto non
signals stored in the memory circuit to become conductive
conductive whereby a third current path bypassing said
whereby said current flows through the current path in
cluding said given data switching means and through said 35 impedance means is provided, output means coupled to
said impedance means and responsive to the magnitude of
impedance means, bypass switching means coupled to
said ?ow of current through said impedance means to de
said current switching means and to said power supply
velop ?rst and second output signals.
means, said bypass switching means ‘being adapted to
5. A read out gate circuit for use with a memory circuit
receive a read signal and ‘being responsive thereto to be
second current paths having normally conductive current
switching means coupled in series with said data switch
come conductive and to render said current switching 40 adapted to store ?rst and second data signals one at a
time, said read out gate circuit including in combination,
means coupled thereto non-conductive whereby a third
power supply means for providing a current coupled to a
current path bypassing said impedance means is pro
reference potential, resistance means coupled to said power
vided, output means coupled to said impedance means and
responsive to the magnitude of said ?ow of current
through said impedance means to develop ‘?rst and second
output signals.
3. A read out gate circuit for use with a memory circuit
adapted to store ?rst and second data signals one at a
time, said read out gate circuit including in combination,
power supply means for providing a current coupled to
a reference potential, impedance means coupled to said
supply means, ?rst data switching means having a control
electrode coupled to the memory circuit for receiving the
?rst data signal and being responsive thereto to become
conductive, said ?rst data switching means further having
an output electrode coupled to the reference potential
and an input electrode, second data switching means hav
ing a control electrode coupled to the memory circuit for
receiving the second data signal and being responsive
thereto to become conductive, said second data switching
means further having an output electrode coupled to said
reference potential and an input electrode, normally con
ductive ?rst and second current switching means each
having an output electrode coupled to said input electrode
of said ?rst and second data switching means respectively
and an input electrode coupled to said resistance means,
said ?rst data switching means and said ?rst current switch
receiving the second data signal and being responsive
thereto to become conductive, said ?rst current path hav 60 ing means forming a ?rst current path and said second
data switching means and said second current switching
ing normally conductive ‘first current switching means
means foming a second current path, a given one of said
coupled in series with said ?rst data switching means and‘
?rst and second data switching means being responsive to
said second current path lhaving normally conductive sec
the particular one of the ?rst and second data signals
ond current switching means coupled in series with said
stored in the memory unit to become conductive whereby
second data switching means, a given one of said ?rst and
said current ?ows through the current path including said
second data switching means being responsive, to the
given data switching means and through said resistance
particular one of the ?rst and second data signals stored in
means, ?rst and second bypass switching means each hav
the memory circuit to become conductive whereby said
ing an output electrode coupled to said output electrode
current ?ows through the current path including said
given data switching means and through said impedance A of said ?rst and second current switching means respec
tively an input electrode coupled to said power supply
means, ?rst and second bypass switching means coupled
means and a control electrode adapted to receive ?rst and
to said ?rst and second current switching means respec
second read signals respectively, each of said ?rst and
tively and to said power supply means, each of said ?rst
second bypass switching means being responsive to the
and second rbypass switching means being adapted to
receive a read signal and being responsive thereto to 75 read signal applied thereto to become conductive and to
power supply means, ?rst and second current paths each
coupled to said impedance means and said reference
potential, said ?rst current path ‘having ?rst data switch
ing means coupled to the memory circuit for receiving
the ?rst data signal and .being responsive thereto to be
come conductive, said second current path having second
data switching means coupled to the memory circuit for
7
3,422,283
render said current switching means coupled thereto non
conductive whereby a third current path bypassing said
resistance means is provided, output means coupled to
said resistance means and responsive to the magnitude of
said ?ow of current though said resistance means to de
8
responsive to the particular one of the ?rst and second
data signals stored in the memory circuit to become con
ductive whereby said current ?ows through the current
path including said given data switching transistor and
6. A read out gate circuit for use with a memory circuit
through said resistance means, ?rst and second bypass
switching transistors each having an emitter electrode
coupled to said emitter electrode of said ?rst current
adapted to store ?rst and second data signals one at a time,
switching transistor a collector electrode coupled to said
velop ?rst and second output signals.
power supply means and base electrodes adapted to re
said read out gate circuit including in combination, power
supply means for providing a current coupled to a ref 10 ceive ?rst and second read signals respectively, a third
bypass switching transistor having an emitter electrode
erence potential, resistance means coupled to said power
coupled to said emitter electrode of said second current
supply means, ?rst data switching means having a control
electrode coupled to the memory circuit for receiving the
switching transistor, a collector electrode coupled to said
?rst data signal and being responsive thereto to become
power supply means and a base electrode adapted to
conductive, said ?rst data switching means further having 15 receive a third read signal, said ?rst, second and third
an output electrode coupled to the reference potential
and an input electrode, second data switching means hav
ing a control electrode coupled to the memory circuit for
receiving the second data signal and being responsive
bypass switching transistors being responsive to said ?rst,
second and third read signals respectively to ‘become con
ductive and to render said current switching transistor
coupled thereto non-conductive, whereby a third current
thereto to become conductive, said second data switching 20 path bypassing said resistance means is provided, output
means coupled to said resistance means and responsive to
means further having an output electrode coupled to said
the magnitude of said flow of current through said resist
reference potential and an input electrode coupled to said
ance means to develop ?rst and second output signals.
resistance means, normally conductive current switching
8. A read out gate circuit for use with a memory cir
means having an output electrode coupled to said input
cuit adapted to store ?rst and second data signals one
electrode of said ?rst data switching means and an input
at a time, said read out gate circuit including in combina
electrode coupled to said resistance means, said ?rst data
tion, power supply means for providing a current coupled
switching means and said current switching means form
to a reference potential, resistance means coupled to said
ing a ?rst current path and said second data switching
power supply means, a ?rst data switching transistor hav
means forming a second current path, a given one of said
ing a base electrode coupled to the memory circuit for
?rst and second data switching means being responsive to
receiving the ?rst data signal and being responsive there
the particular one of the ?rst and second data signals
to to become conductive, said ?rst data switching transis
stored in the memory circuit to become conductive where
tor further having an emitter electrode coupled to the
by said current ?ows through the current path including
reference potential and a collector electrode, a second
said given data switching means and through said re
sistance means, bypass switching means having an output 35 data switching transistor having a base electrode coupled
to the memory circuit for receiving the second data sig
electrode coupled to said output electrode of said current
nal and being responsive thereto to become conductive,
switching means an input electrode coupled to said power
said second data switching transistor further having an
supply means and a control electrode adapted to receive
emitter electrode coupled to said reference potential and
a read signal, said bypass switching means being respon
sive to said read signal to become conductive and to 40 a collector electrode coupled to said resistance means, a
normally conductive current switching transistor having
render said current switching means coupled thereto non
an emitter electrode coupled to said collector electrode of
conductive whereby a third current path bypassing said
said ?rst data switching transistor and a collector elec
resistance means is provided, output means coupled to
trode coupled to said resistance means, said ?rst data
said resistance means and responsive to the magnitude of
said ?ow of current through said resistance means to de 45 switching transistor and said current switching transistor
forming a ?rst current path and said second data switch
velop ?rst and second output signals.
ing transistor forming a second current path, a given one
7. A read out gate circuit for use with a memory cir
of said ?rst and second data switching transistors being
cuit adapted to store ?rst and second data signals one at
responsive to the particular one of the ?rst and second
a time, said read out gate circuit including in ‘combina
tion, power supply means for providing a current coupled 50 data signals stored in the memory circuit to become con
ductive whereby a current ?ows through the current path
to a reference potential, resistance means coupled to said
including said given data switching transistor and through
power supply means, a ?rst data switching transistor hav
said resistance means, a bypass switching transistor having
ing a base electrode coupled to the memory circuit for
an emitter electrode coupled to said emitter electrode of
receiving the ?rst data signal and being responsive thereto
to become conductive, said ?rst data switching transistor 55 said current switching transistor, a collector electrode
coupled to said power supply means and a base electrode
further having an emitter electrode coupled to the refer
adapted to receive a read signal, said bypass switching
ence potential and a collector electrode, a second data
transistor being responsive to said read signal to become
switching transistor having a base electrode coupled to
conductive and to render said current switching transistor
the memory circuit for receiving the second data signal
and being responsive thereto to become conductive, said 60 coupled thereto non-conductive whereby a third current
path bypassing said resistance means is provided, output
second data switching transistor further having an emitter
means coupled to said resistance means and responsive to
electrode coupled to said reference potential and a col
the magnitude of said ?ow of current through said resist
lector electrode, normally conductive ?rst and second cur
ance means to develop ?rst and second output signals.
rent switching transistors each having an emitter electrode
coupled to said collector eectrode of said ?rst and sec 65
No references cited.
ond data switching transistors respectively and a collec
tor electrode coupled to said resistance means, said ?rst
ARTHUR GAUSS, Primary Examiner.
data switching transistor and said ?rst current switching
transistor forming a ?rst current path and said second
R. H. PLOTKIN, Assistant Examiner.
data switching transistor and said second current switch 70
ing transistor forming a second current path, a given one
US. Cl. X.R.
of said ?rst and second data switching transistors being
307-242, 254, 289
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