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DESCRIPTION JP2001021544

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DESCRIPTION JP2001021544
[0001]
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an
ultrasonic probe drive apparatus for producing and outputting a pulse suitable for driving an
ultrasonic probe of an ultrasonic flaw detector.
[0002]
2. Description of the Related Art An ultrasonic probe used in an ultrasonic flaw detector is
manufactured to have a unique frequency band in consideration of the type of an object to be
examined. The specific frequency band is currently roughly divided into three bands according to
the type of subject. Specifically, the characteristic frequency band is about 0.5 to 15 MHz when
the subject is relatively thick and has a large defect (gap) like steel, and the subject is a
component such as a plastic package or FRP. When it is small and thin as a product, about 15 to
50 MHz is used, and when the object is thin and high resolution is required, about 50 to 200
MHz is used.
[0003]
Therefore, in the conventional ultrasonic flaw detection apparatus, usually, a plurality of
ultrasonic probes having different frequency bands are prepared in advance, and one necessary
ultrasonic probe is selected according to the type of the object to be inspected. It was attached to
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and used. On the other hand, in the conventional ultrasonic flaw detection apparatus, in order to
operate the ultrasonic probe attached to the main body of the apparatus, a pulse-like applied
voltage (hereinafter referred to as "pulse") for generating vibration in the piezoelectric element of
the ultrasonic probe is generated. An ultrasonic probe drive for pulse generation is provided. In
the case of an apparatus configuration in which a plurality of prepared ultrasonic probes are
arbitrarily selected and used according to the subject, in the ultrasonic probe drive apparatus,
only one electric circuit for pulse generation is provided, and additionally The one electric circuit
is configured to include at least three capacitors of different capacitances connected in parallel,
and a plurality of switching elements for turning on / off these parallel circuit branches. Then,
according to the frequency band of the ultrasonic probe to be used, the on / off state of the
switching element is selected, thereby selecting the connection state of the three capacitors and
appropriately setting the capacitance as a whole. In order to generate a pulse for driving a
piezoelectric element suitable for each ultrasonic probe, a characteristic curve mainly
representing a charged portion (a negative pulse is used, so a trailing edge representing a rising
state. Hereinafter, the "charge characteristic unit" was adjusted. FIG. 4 shows an example of the
pulse waveform. In waveform 51, the charge characteristic 52 at the trailing edge is adjusted. In
the prior art, the side of the leading edge 53 of the waveform has been set to just fall sharply.
[0004]
Conventionally, in a pulse generation circuit of an ultrasonic probe drive apparatus for
generating vibration in an ultrasonic probe of an ultrasonic flaw detector, a substrate for
mounting this circuit is dimensionally Because of limitations, it has been difficult to construct a
complex circuit that enables fine adjustment of the pulse waveform by providing a large number
of capacitors and switching elements for switching the capacitance. Furthermore, since an
element capable of withstanding relatively high voltages (100 to 300 V or more) must be used as
the switching element, it is not possible to use too many switching elements in terms of circuit
configuration. It has been difficult to construct a complex circuit that allows fine adjustment of
the pulse waveform. Therefore, according to the configuration of the pulse generation circuit of
the conventional ultrasonic probe drive apparatus, although the charge characteristic portion of
the pulse for driving the ultrasonic probe could be roughly adjusted, it was difficult to finely
adjust.
[0005]
Further, with regard to the pulse generation circuit of the ultrasonic probe drive apparatus for
generating vibrations in the ultrasonic probe of the ultrasonic flaw detector, the entire shape of
the pulse waveform, ie, the leading edge of the waveform falling due to the discharge action The
above-mentioned pulse can be finely adjusted by experimentally examining the width (pulse
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width) of the entire waveform consisting of the characteristic portion and the leading edge and
the trailing edge of the waveform rising due to the charging action, thereby making the
ultrasonic probe It is demanded to optimize the pulse to be operated and to improve the
inspection performance.
[0006]
Furthermore, when it is assumed that the number of types of subjects will increase and the
number of specific frequency bands in the ultrasound probe will be further increased in the
future, the inspection performance can not be improved simply by the conventional rough
adjustment. There is a possibility that this will be sufficient, and development of a pulse
generation circuit capable of performing effective fine adjustment is required.
[0007]
An object of the present invention is to solve the above-mentioned problems and to meet the
needs, and it is provided to an ultrasonic probe when the inherent frequency band of the
ultrasonic probe used in the ultrasonic flaw detection apparatus is different. It is an object of the
present invention to provide an ultrasonic probe drive device capable of finely adjusting the
discharge characteristic portion of the pulse and the pulse width and the like according to the
frequency band, thereby improving the inspection performance of the ultrasonic flaw detection
apparatus.
[0008]
SUMMARY OF THE INVENTION In order to achieve the above object, an ultrasonic probe drive
device in an ultrasonic flaw detector according to the present invention is configured as follows.
The ultrasonic probe drive apparatus is configured as a pulse generation circuit for applying a
pulse to the ultrasonic probe of the ultrasonic flaw detector, and the charge characteristic portion
of the pulse is matched to the unique frequency band of the ultrasonic probe. The adjustment
circuit is configured to include a capacitance variable circuit to be adjusted, and further, an
adjustment circuit to adjust the discharge characteristic portion of the pulse is provided.
In the above configuration, the ultrasonic probe drive device has a switching element that
performs switching operation to generate the pulse before the input side charging end of the
capacitance variable circuit, and the adjustment circuit is a switching element. Is a control circuit
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that changes the level of the input signal that controls.
By changing the input signal of the switching element by this control circuit, the output current
of the switching element is controlled to adjust the discharge characteristic portion of the pulse.
In the above configuration, preferably, the control circuit includes a D / A converter, which
converts externally supplied data into an analog signal, and the pulse according to the level of
the analog signal. Configured to adjust the discharge characteristic portion of
[0009]
The ultrasonic probe used in the ultrasonic flaw detector may be one having various frequencies
or one having a frequency slightly deviated from the specified frequency. According to the
ultrasonic probe drive device according to the present invention, a drive pulse for efficiently
giving the striking energy is generated by controlling the discharge characteristic portion of the
pulse with respect to such various ultrasonic probes. Can.
[0010]
BEST MODE FOR CARRYING OUT THE INVENTION Preferred embodiments of the present
invention will be described below based on the attached drawings.
[0011]
FIG. 1 shows an example of a circuit of an ultrasonic probe drive apparatus according to the
present invention for operating an ultrasonic probe of an ultrasonic flaw detector.
In FIG. 1, reference numeral 10 indicated by a broken line block is a driver circuit, and 20 is a
capacitance variable circuit. The driver circuit 10 generates a negative pulse-like applied voltage
(negative pulse) for vibrating the piezoelectric element included in the ultrasonic probe based on
the timing pulse input to the terminal 15 and outputs it to the output terminal 17 It is a circuit.
The electrostatic capacitance variable circuit 20 is a circuit for changing the connection
relationship of the three capacitors to change the combined electrostatic capacitance set in the
circuit and to change the charge characteristic portion of the negative pulse generated at the
output terminal 17 is there.
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[0012]
The driver circuit 10 comprises one transistor 11, three FETs 12, 13, and four resistors R1, R2,
R3, and R4. The input terminal 15 is connected to the gate of the FET 12 via a resistor R2. A
pulse (pulse-like applied voltage) launch timing pulse 16 is constantly input to the input terminal
15 at a preset pulse launch frequency (PRF). The timing pulse 16 is, for example, a pulse having
a pulse width of about 1 μs. When the drain-source of the FET 12 is turned on, a current flows
through the resistor R1, a voltage is applied between the base and the emitter, and the transistor
11 is turned on. When the transistor 11 is turned on, a voltage is applied to the gate of the FET
13 by the voltage drop across the resistor R3, and the FET 13 is turned on. When the FET 13 is
further turned on, a voltage is applied to the gate of the FET 14 by the voltage drop across the
resistor R4, and the FET 14 is turned on. A terminal 17 connected to the drain of the FET 14 is
an output terminal of the driver circuit 10. When the FET 14 is turned on, a pulse for vibrating
the piezoelectric element of the ultrasonic probe is generated at the terminal 17 as described
later.
[0013]
For the driver circuit 10 described above, a series circuit of a D / A converter 19 and an
operational amplifier 21 is connected between another input terminal 18 and a terminal
connected to the emitter of the transistor 11 and the drain of the FET 13. There is. For example,
8-bit digital data d is input to the input terminal 18. The data d is converted to an analog voltage
signal by the D / A converter 19, adjusted in voltage value by the operational amplifier 21, and
applied as voltage signal s1 to the emitter of the transistor 11 and the drain of the FET 13.
Furthermore, the terminal 22 is connected to the drain of the FET 14 of the driver circuit 10, that
is, the terminal 17 via the resistor R5. For example, a voltage of 450 V is always applied to the
terminal 22. The voltage of 450 V is applied to the terminal 17 via the resistor R5 when the FET
14 is in the off state.
[0014]
According to the driver circuit 10 having the above configuration, when the timing pulse 16 is
input to the input terminal 15, it becomes "H" level at the pulse ejection timing, and this is input
to the gate of the FET 12 as described above. Turn on. When the FET 12 is turned on, in the
driver circuit 10, the transistor 11 and the FET 13 are subsequently turned on as described
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above, and finally the FET 14 on the output side is turned on. When the FET 14 is turned on, the
450 V voltage applied to the terminal 17 via the terminal 22 and the resistor R5 drops to the
ground level. Thus, in response to the input of the timing pulse 16, a negative pulse for driving
the ultrasonic probe is produced at the output terminal 17. Also, the discharge characteristic
portion (falling characteristics) and pulse width of the negative pulse are controlled based on the
value of data d input to input terminal 18, but the operation related to data d Will be described in
relation to
[0015]
The variable capacitance circuit 20 is composed of three capacitors C1, C2 and C3 and two relays
23 and 24. The terminal on the input side of the capacitance variable circuit 20 is common to the
output terminal 17 of the driver circuit 10. The capacitors C1 to C3 are connected to form a
parallel positional relationship. The branch of the capacitor C1 is directly connected to its output
terminal 25. The relay 23 is connected in series to the branch of the capacitor C2, and the relay
24 is connected in series to the branch of the capacitor C3. The on / off operation of the relay 23
is controlled by a current signal applied to the control line 26, and the on / off operation of the
relay 24 is controlled by a current signal applied to the control line 27. By appropriately
controlling the on / off operation of relays 23 and 24 according to the purpose, capacitors C1 to
C3 in a parallel connection relationship are arbitrarily combined to form a parallel circuit, and
electrostatics of the respective capacitors are generated. The capacitances are combined, and as a
result, the combined capacitance of the capacitance variable circuit 20 can be changed from the
minimum value (C1) to the maximum value (C1 + C2 + C3).
[0016]
When the FET 14 is off, the voltage at the output terminal 17 of the driver circuit 10 is held at a
potential of 450 V through the resistor R5. At this time, the output terminal 25 of the
capacitance variable circuit 20 is held at the ground level. Next, when the FET 14 is turned off,
discharge occurs and a voltage drop of about -300 V or more occurs from the ground level at the
output terminal 25 of the capacitance variable circuit 20. In addition, a diode 28 connected in a
reverse direction to the output terminal 25 is provided between the output terminal 25 and the
ground terminal, and a diode 28 connected in the forward direction to the output terminal 25
between the output terminal 25 and the final output terminal 31 is provided. A diode 29 is
provided. The diodes 28 and 29 prevent a positive potential from rising at the final output
terminal 31. When a voltage drop of -300 V occurs at the output terminal 25 of the capacitance
variable circuit 20, a negative pulse of about -300 V is output at the final output terminal 31. The
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ultrasonic probe is driven by this negative pulse.
[0017]
The capacitors C1 to C3 appropriately combined in the above-mentioned variable capacitance
circuit 20 start charging at the same time as discharging based on the on operation of the FET 14
is performed. This charging is performed from the circuit element side connected to the terminal
31. Therefore, the potential of the output terminal 25 changes from the falling discharge
characteristic portion (for example, the portion 53 shown in FIG. 4) to the gradually rising
charging characteristic portion (for example the portion 52 shown in FIG. 4). . The abovementioned negative pulse is produced by the discharge characteristic unit and the charge
characteristic unit. In this case, the charge characteristic unit is changed by changing the
combined capacitance set by the capacitance variable circuit 20. Thus, the combined capacitance
by the variable capacitance circuit 20 determines the charging characteristics of the negative
pulse occurring at the output terminal 17 and hence, by changing the combined capacitance, the
charging characteristics of this pulse Can change. Accordingly, the charge characteristic portion
of the negative pulse for operating the ultrasonic probe output from the output terminal 31 is
similarly changed.
[0018]
Next, the operation based on the data d input to the input terminal 18 will be described.
According to the value of data d, the amplitude of the output voltage of D / A converter 19, that
is, the amplitude of voltage signal s1 applied to each of the emitter of transistor 11 and the drain
of FET 13 via op amp 21 is controlled. . When the FET 13 is turned on, a voltage drop occurs in
the resistor R4, and this voltage is applied to the gate of the FET 14, but the voltage applied to
the gate of the FET 14 is changed according to the value of the data d. By controlling the gate
voltage of the FET 14 based on the data d, the drain current of the FET 14 is controlled. Further,
by controlling the drain current of the FET 14, in connection with the combined capacitance set
in the capacitance variable circuit 20, the discharge current in the capacitors C1 to C3 is
controlled, whereby the negative pulse generated at the terminal 17 Fall time (discharge state),
that is, the discharge characteristic portion is changed. The value of data d is selected to be a
large value, and when the gate voltage of FET 14 (specifically, the voltage between the gate and
the source: VGS) is increased, the drain current is increased. That is, when the value of the data d
becomes a large value, a rapid and large falling state is created. On the contrary, when the value
of the data d is selected to be a small value and the gate voltage of the FET 14 becomes low, the
drain current becomes small, so the discharge is performed slowly. That is, a slow and small
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falling state is created.
[0019]
With reference to FIG. 2, the change of the discharge state of the negative pulse occurring at the
terminal 17 depending on the value of the data d, ie the change of the discharge characteristic
part of the negative pulse, will be described. FIG. 2 is a characteristic graph showing the
relationship between the gate-source voltage VGS (horizontal axis) and the drain current ID
(vertical axis) with respect to the FET 14. In this characteristic graph, three graphs at -25 ° C,
25 ° C and 75 ° C are shown. When the gate voltage of the FET 14, that is, the gate-source
voltage VGS is 5.5 V, for example, at 25 ° C., a drain current of about 20 A flows. Assuming that
the on-resistance of the FET 14 is, for example, 1Ω and the combined capacitance is, for
example, 100 pF, the discharge time is 0.1 ns since the discharge is performed with the time
constant of CR. However, in fact, when the charge of 300 V is discharged, the required amount of
300 A (on resistance 1 Ω) is limited to 20 A, so a current of 1/15 flows. Therefore, the discharge
time needs to be 1.5 times, which is about 1.5 ns, and the falling edge of the negative pulse at the
terminal 17 becomes sharp. On the other hand, when VGS is 4 V, for example, the drain current
is about 1.5 A under the same conditions, and a drain current of 1/200 flows as compared with
300 A. Therefore, a discharge time of about 20 ns is required, which is 200 times the time when
VGS is 5.5 V. Thus, as the gate voltage of the FET 14 becomes smaller, the discharge time
becomes longer and the fall of the negative pulse at the terminal 17 becomes loose. However, in
fact, since charging starts simultaneously with discharging, charging catches up earlier, and since
a rising curve is drawn before discharging, the negative pulse amplitude decreases.
[0020]
FIG. 3 shows an example of the negative pulse discharge state generated at the output terminal
17, that is, the waveform in which the discharge characteristic portion changes depending on the
value of the data d. In FIG. 3, (A) shows a waveform when the value of data d is large, that is,
when the gate voltage of FET 14 is large, and (B) shows when the value of data d is an
intermediate value, that is, the gate of FET 14 (C) shows the waveform when the value of the data
d is small, that is, when the gate voltage of the FET 14 is small. As apparent from comparison of
these waveforms, when the gate voltage of the FET 14 is increased, the falling of the pulse
(discharge characteristic portion) becomes steep, the amplitude becomes large, and the rising
becomes steep accordingly. When the gate voltage of the FET 14 is reduced, the fall of the pulse
becomes gentle and the amplitude also decreases. Further, by controlling the discharge
characteristic portion of the negative pulse and controlling the amplitude, the overall pulse width
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of the negative pulse is also controlled. The pulse width narrows as the gate voltage of the FET
14 increases and widens as the gate voltage decreases. Since the gate voltage of the FET 14 is
controlled by the data d, and the data d is 8 bits, the gate voltage of the FET 14 is changed in
256 steps. As a result, the discharge characteristic portion of the negative pulse, the amplitude
and the pulse width are minutely changed in 256 steps. The control of the discharge
characteristic portion and the like of the negative pulse at the terminal 17 is the same as the
discharge characteristic portion and the like of the negative pulse output from the final output
terminal 31.
[0021]
As described above, since the D / A converter 19 etc. is attached to the driver circuit 10 of the
pulse generation circuit and the digital data d of, for example, 8 bits is input to the input terminal
18, ultrasonic probe It is possible to minutely control the fall (discharge characteristic portion) of
the negative pulse for driving the pulse, and minutely control the fall (charge characteristic
portion), and minutely control the pulse width as the entire pulse waveform. As a result, it is
possible to finely control the negative pulse for driving the ultrasonic probe, and it is possible to
give negative pulses having energy-efficient set values to various ultrasonic probes having
different frequencies.
[0022]
As is apparent from the above description, according to the present invention, in the ultrasonic
probe drive apparatus for generating a pulse for driving an ultrasonic probe, the discharge
characteristic portion of the pulse is minutely controlled, Since the adjustment circuit capable of
minutely controlling the pulse width and the charge characteristic portion is provided, the
ultrasonic waves used when the inherent frequency bands of the plurality of ultrasonic probes
installed in the ultrasonic flaw detection apparatus are different. With regard to the probe, the
discharge characteristic portion, pulse width and the like of the pulse supplied to the ultrasonic
probe can be finely adjusted in accordance with the frequency band, whereby the inspection
performance of the ultrasonic flaw detector can be improved.
[0023]
Brief description of the drawings
[0024]
1 is a circuit diagram showing an example of an ultrasonic probe drive device according to the
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present invention.
[0025]
2 is a graph showing the operating characteristics of the FET14.
[0026]
3 is a waveform diagram showing an example of the waveform according to the gate voltage in
the FET14.
[0027]
4 is a waveform diagram showing a negative pulse generated by the conventional ultrasonic
probe drive apparatus.
[0028]
Explanation of sign
[0029]
DESCRIPTION OF SYMBOLS 10 Driver circuit 16 Pulse ejection timing pulse 19 D / A converter
20 Capacitance variable circuit 21 Buffering operational amplifier 23, 24 relay
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