close

Вход

Забыли?

вход по аккаунту

?

DESCRIPTION JP2004222251

код для вставкиСкачать
Patent Translate
Powered by EPO and Google
Notice
This translation is machine-generated. It cannot be guaranteed that it is intelligible, accurate,
complete, reliable or fit for specific purposes. Critical decisions, such as commercially relevant or
financial decisions, should not be based on machine-translation output.
DESCRIPTION JP2004222251
PROBLEM TO BE SOLVED: To obtain a digital amplifier that suppresses pop noise without using a
mute circuit. SOLUTION: A timing control circuit 131 selects one of a music data, a center output
and a lowest output as P output and N output based on a power ON / OFF signal and a start /
stop signal. A selection signal SEL4 is generated to determine whether to output a signal in phase
with the P output or to invert the P output as the 2 and N outputs. The data selection circuit 132
determines the data to be output to the P output and the N output based on the selection signals
SEL1 and SEL2. The output data register circuit 133 converts parallel data determined by the
data selection circuit 132 into serial data and outputs the serial data to the P output. The output
selection circuit 134 determines the N output based on the selection signal SEl4. [Selected figure]
Figure 1
デジタルアンプ
[0001]
The present invention relates to an audio digital amplifier, and more particularly to a pulse width
modulation (PWM) digital amplifier.
[0002]
Devices that operate with batteries and incorporate speakers, such as notebook computers,
portable CDs (Compact Disk) players, DVDs (Digital Versatile Disc) players, car audio devices, etc.,
are in widespread use.
10-04-2019
1
In these devices, not only the quality of sound quality but also miniaturization and power
reduction are required. From such a background, digital amplifiers are drawing attention. Among
them, a digital amplifier of a PWM (Pulse Width Modulation) method used for an application of a
preamplifier for audio can configure all digital signals from the input to the output and can
digitally process all audio signals. In the PWM method, it is also possible to convert the voltage
amplitude of sound information into a digital pulse width and directly drive the speaker, and
there is no need for analog processing. Therefore, it is possible to realize a small-sized amplifier
with low power and a small amount of heat generation.
[0003]
However, in the case of a Bridge-Tied Load (BTL) connection where a PWM digital amplifier and
a speaker are driven by two outputs of positive and negative polarity, a pop noise is generated
when the output of the digital amplifier changes rapidly. There was a problem that.
[0004]
In order to solve such problems, in the prior art, a sawtooth wave and a power supply voltage are
applied at a frequency higher than the frequency of the carrier signal supplied to the pulse width
modulation circuit and in synchronization with the carrier signal. By level comparing the level
with the output of the time constant circuit and supplying the level comparison output and the
output of the pulse width modulation circuit to the exclusive OR circuit, the two outputs are in
phase when the power is turned on and off. It is made to suppress generation | occurrence |
production of a pop sound as it becomes (refer patent document 1), for example.
[0005]
JP 06-196940 A
[0006]
However, in the prior art, when the phase of the output of the exclusive OR is in the transition
state, distortion occurs in the audio signal output to the load.
In order to suppress distortion, there has been a problem that the fixed period during which the
phase of the output of the exclusive OR is transitioning must be muted.
10-04-2019
2
[0007]
In addition, since an integration circuit or a time constant circuit is used, there is also a problem
that processing can not be performed using only digital signals.
[0008]
The present invention has been made in view of the above, and it is an object of the present
invention to obtain a digital amplifier that suppresses pop noise without using a mute circuit.
[0009]
In order to solve the problems described above and to achieve the object, a digital amplifier
according to the present invention pulse-width modulates n (n> 1, n is an integer) bits of sound
data from which quantization noise has been removed by noise shaper Then, in the digital
amplifier that outputs two systems of P output and N output in which the polarity of the P output
is inverted, when the power supply rise is detected, the sound data stop is detected or the power
supply fall is detected. A data selection circuit for increasing or decreasing by one step for each
period of a data setting clock obtained by dividing the P output and the N output by n in a basic
clock of pulse width modulation, and fixing to the center output; Do.
[0010]
According to the present invention, the data selection circuit detects the power supply rise,
detects the sound data stop, or detects the power fall, the P output and the N output are used as
the basic clock of pulse width modulation. Each cycle of the data setting clock divided by n is
increased or decreased by one step and fixed to the center output.
[0011]
According to the digital amplifier according to the present invention, the data selection circuit
pulse-width modulates the P output and the N output when detecting the power supply rise,
detecting the sound data stop, or detecting the power supply fall-down. The basic clock is divided
by n and is increased or decreased by one step for each period of the data setting clock to fix it to
the center output.
As a result, it is possible to suppress abrupt changes in P output and N output at the start of
sound data, and to suppress the occurrence of pop noise without using a mute circuit.
10-04-2019
3
[0012]
Hereinafter, embodiments of a digital amplifier according to the present invention will be
described in detail based on the drawings.
The present invention is not limited by the embodiment.
[0013]
An embodiment of the present invention will be described with reference to FIGS.
FIG. 1 is a block diagram showing the configuration of a digital amplifier 1 according to an
embodiment of the present invention and the configuration of an audio system to which the
digital amplifier 1 is applied.
The audio system using the digital amplifier 1 of this embodiment has a switching element 21 in
which the bridge pre-driver 20 in the BTL circuit 2 is formed of two transistors based on the P
output and N output generated by the digital amplifier 1. The output of the switching element 21
whose high frequency component has been removed by the low pass filter 3 consisting of a coil
and a capacitor drives the speaker 4.
[0014]
The digital amplifier 1 outputs a value of n + 1 with respect to the number n of basic clocks (n>
1, n is an integer) determined by the number of bits of sound data output from the noise shaper
12.
Since the BTL circuit 2 operates with a differential input, the pulse width modulation circuit 13
has two systems of outputs of N output in which the polarities of P output and P output are
inverted.
10-04-2019
4
When the P output is half the number n of basic clocks, that is, n / 2 basic clocks are “1”, this
is the center output of the digital amplifier 1.
[0015]
FIG. 2 shows the P output and the N output of the digital amplifier 1 when the number n of basic
clocks is eight. When the number of basic clocks is eight, assuming that the P output with a cycle
“1” for four basic clocks is the center output “0”, “+1” for the cycle “1” for five basic
clocks, the basic In the case of a cycle "1" for six clocks, it is "+2". Further, when the P output has
a cycle "1" for three basic clocks, it is "-1", and when it has a cycle "1" for two basic clocks, it is "2". The digital amplifier 1 outputs nine steps from the lowest output of “−4” to the highest
output of “+4” by changing the pulse widths of P output and N output, and the speaker 4 via
the BTL circuit 2 Drive to make a sound.
[0016]
The digital amplifier 1 includes a sampling rate converter 10, a volume circuit 11, a noise shaper
12, and a pulse width modulation circuit 13. The sampling rate converter 10 sets a digital signal
recorded at a specific sampling rate on a compact disk (CD), a mini disk (MD), a digital versatile
disc (DVD) or the like to a sampling frequency different from the sampling rate at the time of
recording. Convert. The volume circuit 11 adjusts the volume of the digital signal based on the
external specification. The noise shaper 12 removes quantization noise. The pulse width
modulation circuit 13 performs pulse width modulation processing based on the sound data from
which the quantization noise has been removed by the noise shaper 12.
[0017]
FIG. 3 is a diagram showing the P output and the N output of the pulse width modulation circuit
13 and the output of the BTL circuit 2 when the power is turned on. The pulse width modulation
circuit 13 outputs the P output and the N output in phase as signals at power-on. That is, the
current is not caused to flow to the BTL circuit 2 which operates with the differential input, so
that no sound is generated from the speaker 4. In addition, the pulse width modulation circuit 13
changes P output and N output in the same phase signal one step at a time in the order of -4, -3, -
10-04-2019
5
2, -2, 1 and 10 from the time of power on to fix to center output. Do. As a result, the output of
the BTL circuit 2 gradually changes and is fixed to the center.
[0018]
When the P output and the N output are fixed to the center output, the pulse width modulation
circuit 13 switches the N output from a signal in phase with the P output to a signal obtained by
inverting the P output.
[0019]
When the sound data starts, the pulse width modulation circuit 13 performs pulse width
modulation processing based on the sound data input from the noise shaper 12, and outputs a P
output and an N output to the BTL circuit 2.
The BTL circuit 2 drives the speaker 4 based on the P output and the N output to generate a
sound.
[0020]
FIG. 4 is a diagram showing the P output and N output of the pulse width modulation circuit 13
and the output of the BTL circuit 2 when sound data stops and starts. The pulse width
modulation circuit 13 performs pulse width modulation processing based on sound data input
from the noise shaper 12 until sound data stop, and outputs P output and N output to the BTL
circuit 2. The BTL circuit 2 drives the speaker 4 based on the P output and the N output to
generate a sound.
[0021]
When the sound data is stopped by the stop function or the temporary stop function of the
digital amplifier 1, the pulse width modulation circuit 13 changes the P output as the center
output by changing sequentially one step from the value when the sound data stops. That is,
when P output and N output are +1 to +4 shown in FIG. 2, decrease by one step to center output,
and when P output and N output are -1 to -4, one step each Increase to center output. As a result,
10-04-2019
6
the output of the BTL circuit 2 gradually changes and is fixed at the center.
[0022]
When sound data is started by the reproduction function of the digital amplifier 1, the pulse
width modulation circuit 13 performs pulse width modulation processing based on the sound
data input from the noise shaper 12 and outputs P output and N output to the BTL circuit 2 Do.
The BTL circuit 2 drives the speaker 4 based on the P output and the N output to generate a
sound.
[0023]
FIG. 5 is a diagram showing the P output and the N output of the pulse width modulation circuit
13 and the output of the BTL circuit 2 when the power is turned off. The pulse width modulation
circuit 13 performs pulse width modulation processing based on sound data input from the noise
shaper 12 until sound data stop, and outputs P output and N output to the BTL circuit 2. The BTL
circuit 2 drives the speaker 4 based on the P output and the N output to generate a sound.
[0024]
When the power-down is detected, the pulse width modulation circuit 13 changes the P output as
the center output by sequentially changing one step at a time from the value at which the sound
data has stopped. That is, when P output and N output are +1 to +4 shown in FIG. 2, decrease by
one step to center output, and when P output and N output are -1 to -4, one step each Increase to
center output. As a result, the output of the BTL circuit 2 gradually changes and is fixed at the
center.
[0025]
When the P output and the N output are fixed to the center output, the pulse width modulation
circuit 13 switches the N output from the inverted signal of the P output to a signal in phase with
the P output. Then, the pulse width modulation circuit 13 decreases the P output from the center
output one step at a time to "-4".
10-04-2019
7
[0026]
FIG. 6 is a block diagram showing the configuration of the pulse width modulation circuit 13. The
pulse width modulation circuit 13 includes a timing control circuit 131, a data selection circuit
132, an output data register circuit 133, and an output selection circuit 134.
[0027]
The timing control circuit 131 generates the data setting clock CLK 8 and the selection signals
SEL 0 to 4 based on the clock CLK, the power ON / OFF signal, and the start / stop signal. Then,
the selection signals SEL 0 to 2 and the data setting clock CLK 8 are output to the data selection
circuit 132, the selection signal SEL 3 to the output data register circuit 133, and the selection
signal SEL 4 to the output selection circuit 134.
[0028]
The data selection circuit 132 selects either the 8-bit sound data DATA0 to 7 input from the
noise shaper 12 based on the selection signals SEL0 to 2 or predetermined data for removing
pops, and the selected output The PWMs 0 to 7 are output to the output data register circuit
133.
[0029]
FIG. 7 is a diagram showing an example of a circuit of data selection circuit 132 shown in FIG.
The data selection circuit 132 includes an IV 41 which is an inversion circuit, AND 50 to 65
which are AND gates, selectors 70 to 73 which are selection circuits, and flip flops 80 to 87 with
a set function. When the selection signal SEL0 is "1" and the selection signal SEL1 is "1", the
output of the AND 65 becomes "1", and the AND 50 to 57 select the sound data DATA 0 to 7 to
the flip flops 80 to 87 with set function. Set DATA 0-7. Thereby, the data selection circuit 132
outputs the sound data DATA 0 to 7 to the outputs PWM 0 to 7.
10-04-2019
8
[0030]
The selection signal SEL2 is effective when the selection signal SEL1 is "0". When the selection
signal SEL1 is "0" and the selection signal SEL2 is "1", the flip-flops 80 to 87 with set function are
connected in the order of the flip-flops 80, 81, 82,. An eight-step shift register is configured to
shift data at the rising edge of. Since the fixed value "0" is input to the terminal D of the set
function-equipped flip-flop 80, the output PWM7 to 0 is "1110000", "11100000", for example,
when it is "1111000" by the shift operation. ..., it changes as "00000000". That is, the values of
the outputs PWM7 to 0 are changed by one step to "00000000".
[0031]
When the selection signal SEL1 is "0" and the selection signal SEL2 is "0", the flip-flops 80 to 83
with set function are connected in the order of the flip-flops 80, 81, 82, 83 with set function.
Construct a four-stage shift register that shifts data at the rising edge. The set function-provided
flip flops 84 to 87 are connected in the order of the set function provided flip flops 87, 86, 85,
84, and constitute a four-stage shift register that shifts data at the rise of the data setting clock
CLK8. Since "1" is input to the terminal D of the set function flip-flop 87, the outputs PWM7 to 4
change to "1000", "1100", "1110", "1111" and the like. Further, since “0” is input to the
terminal D of the set function provided flip flop 80, the outputs PWM3 to 0 become “0000”.
That is, when the selection signal SEL1 is “0” and the selection signal SEL2 is “0”, the
outputs PWM7 ~0 are changed by one step to become the value of the center output.
[0032]
The output data register circuit 133 latches the outputs PWM0 to PWM7 of the data selection
circuit 132 based on the selection signal SEL3 and synchronizes the latched outputs PWM0 to
PWM7 with the clock CLK in the order of the outputs PWM0, PWM1,. Output as P output signal
one bit at a time. That is, the parallel outputs PWM0 to PWM7 latched based on the selection
signal SEL3 are converted into serial data.
[0033]
FIG. 8 is a diagram showing an example of the output data register circuit 133 shown in FIG. The
10-04-2019
9
output data register circuit 133 includes flip-flops 90 to 97 with a selector function. The selectorfunctioned flip flops 90 to 97 select the data inputted to the terminal D2 when the terminal SEL
is "1", and select the data inputted to the terminal D1 when the terminal SEL is "0". , In
synchronization with the rise of the terminal CK.
[0034]
The flip-flops 90 to 97 with a selector function are connected in the order of the flip-flops 97, 96,
95,... 90 with a selector function, and form an 8-stage shift register that shifts data in
synchronization with the rising of the clock CLK.
[0035]
The output selection circuit 134 selects whether to output the P output signal as it is as it is or to
invert the P output signal as the N output signal, based on the selection signal SEL4.
That is, it is selected whether to make the N output be a signal in phase with the P output or to
make the P output inverted.
[0036]
Next, the operation of the pulse width modulation circuit 13 will be described with reference to
time charts of FIGS. 9 to 12. First, the normal operation will be described with reference to the
time chart of FIG.
[0037]
In the normal operation of outputting the sound data DATA7 to 0 input from the noise shaper
12, the timing control circuit 131 sets the selection signal SEL1 to "1", the selection signal SEL2
to "0", and the selection signal SEL4. Set to "1". Further, the data setting clock CLK8 obtained by
dividing the clock CLK by 8 is output in synchronization with the falling of the clock CLK. The
sound data DATA7 to DATA0 are input in synchronization with the falling of the clock CLK every
eight cycles of the clock CLK. The timing control circuit 131 outputs the data setting clock CLK8
so that the data setting clock CLK8 rises 7 cycles after the clock CLK after the change point of
10-04-2019
10
the sound data DATA7-0. The timing control circuit 131 selects the selection signal SEL0 for one
cycle of the clock CLK in synchronization with the rising of the clock CLK 1.5 cycles after the
rising of the data setting clock CLK8 every cycle of the data setting clock CLK8. Make it 1 ”.
That is, the selection signal SEL0 becomes "1" for one cycle of the clock CLK after a half cycle of
the clock CLK from the change point of the sound data DATA7.about.0. Further, the timing
control circuit 131 synchronizes the selection signal SEL3 for one cycle of the clock CLK in
synchronization with the falling of the clock CLK one cycle after the clock of the data setting
clock CLK8 every cycle of the data setting clock CLK8. Set to "0". That is, the selection signal
SEL3 becomes "0" for one cycle of the clock CLK from the change point of the sound data
DATA7.about.0. The timing of the data setting clock CLK8, the selection signals SEL0 to 2, and
the data setting clock CLK8 is the timing constraint condition of the flip flops 80 to 87 with set
function (recovery time, removal time, setup time, hold time, pulse It is assumed that the
selection signal SEL3 is generated so as to satisfy the timing constraints of the flip flops 90 to 97
with a selector function.
[0038]
At time t1, the sound data DATA7 to 0 change to "11100000". At time t2, the selection signal
SEL0 becomes "1". Since the selection signal SEL0 is “1” and the selection signal SEL1 is “1”,
the output of the AND 65 becomes “1”, and the AND 50 through 57 set the sound data DATA
7 through 0 to the flip-flop with setting function 87 80 Output to the terminal S of As a result,
"1" is input to the terminal S of the set function flip flops 87 to 85, "0" is input to the terminals S
of the set function flip flops 84 to 80, and the PWMs 7 to 0 become "11100000". . That is, sound
data DATA7-0 are output to PWM7-0.
[0039]
Further, since the selection signal SEL3 is "0", the flip-flops 97 to 90 with a selector function
latch the outputs PWM7 to PWM0. Then, the value of the output PWM0 (in this case, "0") is
output to the P output. At time t3 which is the next rise of the clock CLK, since the selection
signal SEL3 is "1", the grip flops 97 to 90 with a selector function operate as shift registers. That
is, the P output is made "0", "0", "0", "0", "0", "0", "1", "1", "1" in synchronization with the rise of
the clock until time t4b.
[0040]
Since the selection signal SEL4 is "1", the output selection circuit 134 outputs a signal obtained
10-04-2019
11
by inverting the P output to the N output.
[0041]
At time t4a, the data setting clock CLK8 changes from "0" to "1".
At this time, since the selection signal SEL0 is "0", the output of the AND 65 is "0". Therefore, the
ANDs 50 to 57 output "0" to the terminals S of the set-function-equipped flip-flops 87 to 80.
Further, since the selection signal SEL1 is "1", "0" is input to the ANDs 58 to 64 through the IV
41, and "0" is input to the terminal D of the flip-flops 81 to 87 with set function. The terminal D
of the set function-equipped flip flop 80 is fixed at "0". Since the terminal S is "0", the flip-flops
80 to 87 with set function latch the "0" input to the terminal D at the rising edge when the data
setting clock CLK8 changes from "0" to "1". Output. As a result, all the outputs of the flip-flops 80
to 87 with a setting function become "0", which means that the sound data DATA7 to 0 set at
time t2 are reset.
[0042]
The data selection circuit 132 and the output data register circuit 133 repeat such operation, and
output the sound data DATA7 to 0 inputted from the noise shaper 12 to the P output and the N
output.
[0043]
Next, with reference to the time chart of FIG. 10, the operation of the pulse width modulation
circuit 13 at the time of power on will be described.
When the timing control circuit 131 detects that the power supply has risen by the power ON /
OFF signal, it sets the selection signals SEL1, 2, 4 to "0". Further, the data setting clock CLK8
obtained by dividing the clock CLK by 8 is output in synchronization with the falling of the clock
CLK. The timing control circuit 131 sets the selection signal SEL0 to "1" for one cycle of the clock
CLK in synchronization with the rising of the clock CLK every cycle of the data setting clock
CLK8. Further, the selection signal SEL3 is set to "0" for one cycle of the clock CLK in
synchronization with the falling edge of the clock CLK every cycle of the data setting clock CLK8.
10-04-2019
12
[0044]
Since the selection signal SEL1 is "0", the output of the AND 65 becomes "0", and the AND 50 to
57 output "0" to the terminal S of the flip-flops 80 to 87 with set function. Thereby, the flip-flops
80 to 87 with set function latch and output the data input to the terminal D at the rising edge of
the clock input to the terminal CK. Since the selection signal SEL2 is "0", the set functionequipped flip-flops 87 to 84 operate as a four-stage shift register.
[0045]
At time t5, when the data setting clock CLK8 rises, the flip flops 80 to 83 with set function shift
data. Also, the flip-flops 87 to 84 with set function shift data. Since the set function flip flop 80
latches "0" and the set function flip flop 87 latches "1", the outputs PWM7 to 0 become
"10000000".
[0046]
At time t6, since the selection signal SEL3 is "0", the flip-flops 97 to 90 with a selector function
latch the outputs PWM7 to PWM0. Then, the value of the output PWM0 (in this case, "0") is
output to the P output. At time t7, which is the next rise of the clock CLK, since the selection
signal SEL3 is "1", the flip-flops 97 to 90 with a selector function operate as shift registers. That
is, the P output is set to "0", "0", "0", "0", "0", "0", "0", "0", "1" in synchronization with the rise of
the clock until time t9.
[0047]
At time t8, the selection signals SEL1 and SEL2 do not change from time t5, so the data selection
circuit 132 operates in the same manner as at time t5. That is, when the data setting clock CLK8
rises, the flip-flops 80 to 83 with set function shift data. Also, the flip-flops 87 to 84 with set
function shift data. Since the set function flip-flop 80 latches “0” and the set function flip flop
87 latches “1”, the outputs PWM7 ~0 become “11000000”.
10-04-2019
13
[0048]
At time t9, the flip-flops 97 to 90 with a selector function operate in the same manner as at time
t6 and latch the outputs PWM7 to PWM0. Then, the outputs PWM0, 1,..., 7 are output in
synchronization with the rise of the clock CLK in order. That is, the P output is made "0", "0", "0",
"0", "0", "0", "0", "1", "1" in synchronization with the rise of the clock.
[0049]
The data selection circuit 132 and the output data register circuit 133 repeat such an operation
until time t11 when the selection signal SEL1 is "1", and change the P output one step at a time
to fix it at the center output.
[0050]
Since the selection signal SEL4 is "0" until time t10, the output selection circuit 134 outputs a
signal in phase with the P output to the N output.
[0051]
The timing control circuit 131 sets the selection signal SEL4 to "1" at time t10.
That is, the timing control circuit 131 sets the selection signal SEL4 to "1" after the P output is
fixed to the center output (in this case, four cycles or more from the first rise of the data setting
clock CLK8).
[0052]
When the selection signal SEL4 becomes "1", the output selection circuit 134 outputs a signal
obtained by inverting the P output to the N output.
[0053]
After setting the selection signal SEL4 to "1", the timing control circuit 131 sets the selection
signal SEL1 to "1" at a predetermined timing.
10-04-2019
14
In the case of the timing chart of FIG. 10, the timing control circuit 131 sets the selection signal
SEL1 to “1” at time t11.
That is, the timing control circuit 131 sets the selection signal SEL1 to “1” after setting the
selection signal SEL4 to “1” and inverting the N output to “1” after the P output is fixed to
the center output and then the normal mode. Make it As a result, the P output and the N output
become outputs based on the sound data DATA7-0.
[0054]
Next, with reference to FIG. 11, the operation of the pulse width modulation circuit 13 when the
sound data is temporarily stopped and reproduction is started will be described. The pulse width
modulation circuit 13 operates normally until time t12. That is, the pulse width modulation
circuit 13 outputs a P output and an N output based on the sound data DATA7-0.
[0055]
When the stop of the sound data is detected by the start / stop signal at time t12, the timing
control circuit 131 sets the selection signal SEL1 to "0".
[0056]
While the selection signal SEL1 is "0", the output of the AND 65 is "0" without being affected by
the selection signal SEL0, and the AND 50 to 57 are "0" at the terminal S of the flip-flops 80 to
87 with set function. Output
Thereby, the flip-flops 80 to 87 with set function latch and output the data input to the terminal
D at the rising edge of the clock input to the terminal CK. Since the selection signal SEL2 is "0",
the set function-equipped flip-flops 87 to 84 operate as a four-stage shift register.
[0057]
10-04-2019
15
At time t13, when the data setting clock CLK8 rises, the flip flops 80 to 83 with set function shift
data. Also, the flip-flops 87 to 84 with set function shift data. Since the immediately preceding
output PWM7 to 0 is "11000000", the set function flip flop 80 latches "0" and the set function
flip flop 87 latches "1", so the output PWM7 to 0 becomes "11100000" .
[0058]
At time t14, since the selection signal SEL3 is "0", when the clock CLK rises, the flip-flops 97 to
90 with a selector function latch the outputs PWM7 to PWM0. Then, the value of the output
PWM0 (in this case, "0") is output to the P output. Since the select signal SEL3 is "1" at time t15,
which is the next rise of the clock CLK, the flip-flops 97 to 90 with a selector function operate as
shift registers. That is, the P output is set to "0", "0", "0", "0", "0", "1", "1", "1", "1" in
synchronization with the rise of the clock until time t17.
[0059]
At time t17, the flip-flops 97 to 90 with a selector function operate in the same manner as at
time t4b, and latch the outputs PWM7 to PWM0. Then, the outputs PWM0, 1,..., 7 are output in
synchronization with the rise of the clock CLK in order. That is, the P output is made "0", "0", "0",
"0", "1", "1", "1", "1", "1" in synchronization with the rising of the clock.
[0060]
The data selection circuit 132 and the output data register circuit 133 repeat such an operation
until time t18 when the selection signal SEL1 is "1", and change the P output one step at a time
to fix it at the center output. During this time, since the selection signal SEL4 is "1", the output
selection circuit 134 outputs a signal obtained by inverting the P output to the N output.
[0061]
When the start of sound data is detected by the start / stop signal at time t18, the timing control
circuit 131 sets the selection signal SEL1 to "1". As a result, the normal operation mode is set,
10-04-2019
16
and the P output and the N output based on the sound data DATA 7 to 0 are obtained.
[0062]
Next, the operation of the pulse width modulation circuit 13 at power-on will be described with
reference to the time chart of FIG. The pulse width modulation circuit 13 normally operates until
time t19. That is, the pulse width modulation circuit 13 outputs P and N based on the sound data
DATA7-0.
[0063]
At time t19, when the power ON / OFF signal changes from "0" to "1", that is, when it is detected
that the power supply falls, the timing control circuit 131 sets the selection signal SEL1 to "0".
[0064]
While the selection signal SEL1 is "0", the output of the AND 65 is "0" without being affected by
the selection signal SEL0, and the AND 50 to 57 are "0" at the terminal S of the flip-flops 80 to
87 with set function. Output
Thereby, the flip-flops 80 to 87 with set function latch and output the data input to the terminal
D at the rising edge of the clock input to the terminal CK. Since the selection signal SEL2 is "0",
the set function-equipped flip-flops 87 to 84 operate as a four-stage shift register.
[0065]
At time t20, when the data setting clock CLK8 rises, the flip flops 80 to 83 with set function shift
data. Also, the flip-flops 87 to 84 with set function shift data. Since the immediately preceding
output PWM7 to 0 is "11100000", the set function flip flop 80 latches "0" and the set function
flip flop 87 latches "1", so the output PWM7 to 0 becomes "111 10000" .
[0066]
10-04-2019
17
At time t21, since the selection signal SEL3 is "0", when the clock CLK rises, the flip-flops 97 to
90 with a selector function latch the outputs PWM7 to PWM0. Then, the value of the output
PWM0 (in this case, "0") is output to the P output. At time t22, which is the next rise of the clock
CLK, since the selection signal SEL3 is "1", the flip-flops 97 to 90 with a selector function operate
as shift registers. That is, the P output is made "0", "0", "0", "0", "1", "1", "1", "1", "1" in
synchronization with the rising of the clock.
[0067]
The timing control circuit 131 sets the selection signal SEL4 to "0" at time t23. That is, the timing
control circuit 131 sets the selection signal SEL4 to "0" after the P output is fixed to the center
output (in this case, four cycles or more from the first rise of the data setting clock CLK8).
[0068]
When the selection signal SEL4 becomes "0", the output selection circuit 134 outputs a signal in
phase with the P output to the N output.
[0069]
The timing control circuit 131 sets the selection signal SEL2 to “1” at time t24 after setting the
selection signal SEL4 to “0”.
Since the selection signal SEL1 is "0", when the selection signal SEL2 becomes "1", the flip-flops
80 to 87 with a set function become eight-stage shift registers.
[0070]
At time t25, when the data setting clock CLK8 rises, the flip flops 80 to 87 with a set function
shift data. Since the set function-equipped flip-flop 80 latches "0", the outputs PWM7-0 become
"11100000".
10-04-2019
18
[0071]
At time t26, since the selection signal SEL3 is "0", when the clock CLK rises, the flip-flops 97 to
90 with a selector function latch the outputs PWM7 to PWM0. Then, the value of the output
PWM0 (in this case, "0") is output to the P output. At time t27, which is the next rise of the clock
CLK, since the selection signal SEL3 is "1", the flip-flops 97 to 90 with a selector function operate
as shift registers. That is, the P output is made “0”, “0”, “0”, “0”, “0”, “1”, “1”,
“1” in synchronization with the rise of the clock.
[0072]
The data selection circuit 132 and the output data register circuit 133 repeat such an operation
to change the P output step by step to make "-4" (see FIG. 2).
[0073]
As described above, in this embodiment, when the power is turned on, the N output is made to be
in phase with the P output and the N output and the P output are changed one step at a time and
fixed to the center output. After being fixed to the center output, the N output is switched to the
output obtained by inverting the polarity of the P output.
As a result, the BTL circuit driven by the digital amplifier smoothly rises, and can be changed to
the center output without noise generation, and the sound data starts from the center output, so
pop does not occur using the mute circuit. Noise can be removed to start reproduction of sound
data.
[0074]
At power down, P output and N output are changed one step at a time and fixed to the center
output, then N output is output in phase with P output and P output and N output are decreased
one step at a time Pop noise can be reduced since the lowest output is used.
[0075]
Furthermore, at the time of sound data stop, the P output and the N output are changed one step
10-04-2019
19
at a time and fixed to the center output.
That is, the P output and the N output are set to be the center output. As a result, without using a
mute circuit, it is possible to suppress the occurrence of a sudden change at the start of sound
data and to start reproduction of sound data without generating pop noise.
[0076]
Note that a noise shaper clock may be used instead of the data setting clock. Thereby, the P
output and the N output can be changed to the center output or the lowest output in
synchronization with the noise shaper, and further, pop noise can be suppressed.
[0077]
Further, the circuit driven by the digital amplifier according to the present invention is not
limited to the BTL circuit, and may be a circuit driven by a differential input such as an
operational amplifier circuit or a filter circuit.
[0078]
As described above, the digital amplifier according to the present invention is useful for a pulse
width modulation type digital amplifier, and is particularly suitable for BTL connection of a
digital amplifier and a speaker.
[0079]
BRIEF DESCRIPTION OF THE DRAWINGS It is a block diagram which shows the structure of the
digital amplifier of embodiment in this invention, and the structure of the audio system to which
a digital amplifier is applied.
It is a figure which shows P output and N output of a digital amplifier.
It is a figure which shows the output of P output and N output of a pulse width modulation
circuit at the time of power supply start-up, and a BTL circuit. FIG. 7 is a diagram showing the P
10-04-2019
20
output and N output of the pulse width modulation circuit and the output of the BTL circuit when
sound data stops and starts. It is a figure which shows the output of P output and N output of a
pulse width modulation circuit at the time of power supply stop, and a BTL circuit. It is a block
diagram which shows the structure of a pulse width modulation circuit. It is a figure which shows
an example of a data selection circuit. It is a figure which shows an example of an output data
register circuit. It is a time chart for explaining the operation of the pulse width modulation
circuit at the time of normal operation. It is a time chart for explaining operation of a pulse width
modulation circuit at the time of power supply startup. It is a time chart for explaining the
operation of a pulse width modulation circuit when sound data stops and starts. It is a time chart
for explaining the operation of the pulse width modulation circuit at the time of power supply
shutdown.
Explanation of sign
[0080]
Reference Signs List 1 digital amplifier 2 BTL circuit 3 low pass filter 4 speaker 10 sampling rate
converter 11 volume circuit 12 noise shaper 13 pulse width modulation circuit 20 bridge predriver 21 switching element 41 inverting circuit 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61,
62, 63, 64, 65 And gate 70, 71, 72, 73 Selector 80, 81, 82, 83, 84, 85, 86, 87 Flip with set
function 90, 91, 92, 93, 94, 95, 96, 97 Flip-flops with selector function 131 Timing control
circuit 132 Data selection circuit 133 Output data register circuit 134 Output selection circuit
10-04-2019
21
Документ
Категория
Без категории
Просмотров
0
Размер файла
32 Кб
Теги
description, jp2004222251
1/--страниц
Пожаловаться на содержимое документа