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DESCRIPTION JP2006311361

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DESCRIPTION JP2006311361
PROBLEM TO BE SOLVED: When software controlling a gain of an audio signal amplifier by a
microcomputer, there arises a problem that a load on the microcomputer becomes heavy.
SOLUTION: An attenuator 100 attenuates and outputs an input signal Vin to an amplifier 30
which amplifies signals applied to two input terminals. In the resistor group 10, a plurality of
resistors R1 to Rn are connected in series, an input signal Vin is applied to one end, and the other
end is grounded. The switch group 12 includes a plurality of switches, and connects the first
output terminal 106 and the second output terminal 108 to the connection nodes N1 to Nn. The
comparison / determination circuit 18 compares the data variable Dy corresponding to the
current attenuation factor with the target data Dx corresponding to the target attenuation factor,
and outputs an up signal or a down signal. The decoder circuit 14 selects one of the first and
second switch groups SWa and SWb corresponding to the digital data Dy output from the up /
down counter 16 one by one and turns it on. [Selected figure] Figure 2
Attenuator, variable gain amplifier and electronic device using the same
[0001]
The present invention relates to gain control techniques for variable gain amplifiers.
[0002]
In audio equipment, an audio signal amplifier is used to amplify an audio signal, which is a weak
electrical signal, and supply it to an audio output unit such as a speaker or earphone.
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In such audio signal amplifiers, their gain is varied to adjust the volume. For example, a variable
gain amplifier described in Patent Document 1 is used to adjust the volume.
[0003]
In the audio signal amplifier, when the amplitude of the signal becomes discontinuous when
changing the gain, unpleasant noise known as click sound is generated from the speaker and
stimulates the human auditory sense of listening to the audio.
[0004]
In order to reduce such click noise, it is necessary to gradually change the gain of the audio
signal amplifier.
In order to slowly change the gain of the audio signal amplifier, a time constant circuit with a
capacitor is used. The time constant circuit generates a voltage which rises or falls with a certain
time constant by charging and discharging the capacitor, and controls the gain of the audio
signal amplifier based on this voltage.
[0005]
JP 2004-336129 A
[0006]
Here, gain control of the audio signal amplifier is considered.
A microcomputer is mounted on the electronic device on which the audio signal amplifier is
mounted, and the gain of the audio signal amplifier is controlled by the microcomputer. Here, in
the conventional audio signal amplifier, the case of largely switching the gain will be considered.
For example, when switching the gain of an audio signal amplifier whose gain can be switched in
50 steps from the maximum gain to the minimum gain, the audio signal is distorted if it is
switched at one time. Therefore, in order to prevent distortion of the audio signal, the
microcomputer performs control to switch the gain stepwise. However, when software
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controlling the gain of the audio signal amplifier with a microcomputer, there arises a problem
that the load on the microcomputer becomes heavy.
[0007]
The present invention has been made in view of these problems, and an object thereof is to
provide an attenuator and a variable gain amplifier in which the attenuation factor or gain can be
switched stepwise inside the circuit.
[0008]
One aspect of the present invention relates to an attenuator that attenuates and outputs an input
signal to an amplifier that amplifies signals applied to two input terminals.
The attenuator includes first and second output terminals to be respectively connected to the two
input terminals of the amplifier, a data variable corresponding to the current attenuation factor,
and target data corresponding to the target attenuation factor. The comparison / determination
circuit that compares and outputs an up signal or down signal, and the up / down counter that
increases / decreases the data variable based on the up / down signal output from the
comparison / determination circuit. Output signals attenuated at different attenuation rates to
the first and second output terminals, respectively.
[0009]
According to this aspect, by giving only target data corresponding to the target attenuation rate
from the outside, the attenuation rate changes stepwise, so that distortion of the signal can be
reduced. Note that in this specification, the input terminal or the output terminal does not mean a
pad of an LSI, but means one point on a circuit.
[0010]
Another aspect of the present invention also relates to an attenuator for attenuating and
outputting an input signal to an amplifier that amplifies signals applied to two input terminals. In
this attenuator, a plurality of resistors are connected in series with first and second output
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terminals to be respectively connected to two input terminals of the amplifier, and an input
signal is applied to one end, and the other end is grounded. A group of switches, a first switch
group including a plurality of switches provided between connection nodes of the first output
terminal and the plurality of resistors, and a plurality of switches provided between connection
nodes of the second output terminal and the plurality of resistors; Comparison determination
circuit that compares the two switches, the data variable corresponding to the current
attenuation rate, and the target data corresponding to the attenuation rate to be the target value,
and outputs the up signal or the down signal, and the output from the comparison determination
circuit An up / down counter that increases / decreases the data variable based on the up signal
and the down signal, and a switch corresponding to the data variable output from the up / down
counter from the first and second switch groups One by one select and comprises a decoder
circuit for turning on and.
[0011]
According to this aspect, by controlling the selection of the switch by the decoder circuit, it is
possible to control the voltage division ratio of the resistor and to change the attenuation factor
stepwise.
[0012]
The plurality of switches respectively included in the first switch group and the second switch
group may be alternately connected to connection nodes of the plurality of resistors included in
the resistor group.
In this case, since one switch is connected to the connection node of the plurality of resistors, it is
possible to suppress an increase in circuit scale and to improve the wiring efficiency.
[0013]
The counting step of the up / down counter may be variable. By controlling the counting step
according to the amplitude of the input signal, it is possible to make the change of the
attenuation factor close to the desired curve.
[0014]
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The attenuator may further comprise a register circuit for holding target data. In this case, if
desired target data is externally written to the register circuit by a microcomputer or the like, the
attenuation factor of the attenuator gradually approaches the value corresponding to the target
data.
[0015]
Another aspect of the invention is a variable gain amplifier. The variable gain amplifier
corresponds to the attenuator described above, a first differential pair corresponding to the first
noninverting input terminal and the first inverting input terminal, and a second noninverting
input terminal and the second inverting input terminal. From the output terminal of the
operational amplifier to the first and second inverting input terminals, and an operational
amplifier including a second differential pair and a current mirror load commonly provided to the
first and second differential pairs And a return path leading to The first and second output
terminals of the attenuator are connected to the first and second non-inverting input terminals of
the operational amplifier, and the signal to be amplified by the variable gain amplifier is input to
the attenuator as an input signal. .
[0016]
The operational amplifier alternately switches active differential pairs according to a
predetermined time constant. According to this aspect, since the amplitude of the signal input to
the operational amplifier is gradually switched, the amplitude of the signal can be changed
gradually.
[0017]
Yet another aspect of the present invention is also a variable gain amplifier. The variable gain
amplifier corresponds to the attenuator described above, a first differential pair corresponding to
the first noninverting input terminal and the first inverting input terminal, and a second
noninverting input terminal and the second inverting input terminal. And an operational
amplifier including a second differential pair and a current mirror load commonly provided to the
first and second differential pairs. The first and second non-inverting input terminals of the
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operational amplifier receive the signal to be amplified by the variable gain amplifier, and the
first and second inverting input terminals include first and second output terminals of the
attenuator. Connected
[0018]
By using the above-described attenuator as a feedback resistor provided between the output
terminal and the inverting input terminal of the operational amplifier, it is possible to configure a
non-inverted variable gain amplifier and to switch its gain gradually.
[0019]
Yet another aspect of the present invention is also a variable gain amplifier.
This variable gain amplifier has a first differential pair associated with the first non-inverted
input terminal and the first inverted input terminal, and a second difference associated with the
second non-inverted input terminal and the second inverted input terminal. A plurality of
resistors are connected in series with an operational amplifier including a dynamic pair and a
current mirror load commonly provided to the first and second differential pairs, an input signal
is applied to one end, and the other end is an operation Between a feedback resistor connected to
the output terminal of the amplifier, a voltage source for applying a reference voltage to the first
and second noninverting input terminals of the operational amplifier, and a connection node
between the first inverting input terminal of the operational amplifier and a plurality of resistors
And a second switch group including a plurality of switches provided between a connection node
of the second inverting input terminal of the operational amplifier and the plurality of resistors,
and the current gain. Data variable and target gain A comparison / determination circuit that
compares the corresponding target data and outputs an up signal or a down signal, an up / down
counter that increases / decreases a data variable based on the up signal / down signal output
from the comparison / determination circuit, And a decoder circuit which selects one of the
switches corresponding to the data variable output from the up / down counter one by one from
the second switch group and turns it on.
[0020]
According to this aspect, in the inverting variable gain amplifier including the feedback resistor
between the output terminal and the inverting input terminal of the operational amplifier, the
gain is obtained by switching the resistance division ratio of the feedback resistor according to
the output of the up / down counter. Can be switched slowly.
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[0021]
The bias currents of the first and second differential pairs of the operational amplifier may be
controlled in synchronization with the up / down counter.
In this case, since the active differential pair of the operational amplifier is controlled in
synchronization with the up / down counter, the gain of the variable gain amplifier can be
switched more smoothly.
[0022]
An audio signal may be input to the variable gain amplifier as a signal to be amplified. In this
case, the gain of the variable gain amplifier corresponds to the volume. By gradually changing
the gain of the variable gain amplifier, distortion of the audio signal can be reduced when
switching the volume.
[0023]
The variable gain amplifier may be integrated on one semiconductor substrate.
[0024]
Yet another aspect of the present invention is an electronic device.
The electronic apparatus includes an audio output unit, the above-described variable gain
amplifier that outputs an amplified audio signal to the audio output unit, and a microcomputer
that instructs the variable gain amplifier to have a gain corresponding to a volume. The audio
output unit includes a speaker, an earphone, and the like. According to this aspect, if the volume
value after change is set by the microcomputer, the variable gain amplifier switches the gain
stepwise until the volume is achieved, so that the load on the microcomputer can be reduced and
unnecessary from the audio output unit Noise can be prevented.
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[0025]
It is to be noted that arbitrary combinations of the above-described components, and components
obtained by replacing the components and expressions of the present invention among methods,
apparatuses, systems, and the like are also effective as aspects of the present invention.
[0026]
According to the attenuator and the variable gain amplifier according to the present invention,
the attenuation factor or the gain can be switched stepwise in the circuit, and the load of an
external microcomputer or the like can be reduced.
[0027]
FIG. 1 is a block diagram showing a configuration of an audio signal output device in which a
variable gain amplifier according to the present embodiment is used.
The audio signal output device 1000 includes a variable gain amplifier 200, a power amplifier
202, a D / A converter 210, a reproduction device 220, a microcomputer 230, and a speaker
SP1.
This audio signal output device is used, for example, as a car audio system. The playback device
220 is a CD player, an MD player, or another digital audio player, and reads audio data recorded
as digital data on a disc or the like. The playback device 220 outputs a digital signal SIG1
obtained by decoding the read digital data to the D / A converter 210. The D / A converter 210 D
/ A converts the digital signal SIG1 and outputs it as an analog signal SIG2.
[0028]
Variable gain amplifier 200 amplifies analog signal SIG 2 and outputs it to power amplifier 202.
The gain of the variable gain amplifier 200 is controlled by the microcomputer 230 by the
volume control signal VOL. The power amplifier 202 amplifies the analog signal SIG3 output
from the variable gain amplifier 200, and drives the speaker SP1. By changing the gain of the
variable gain amplifier 200, the amplitudes of the input and output signals of the power amplifier
202 are controlled, and the volume of the sound output from the speaker SP1 is adjusted.
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[0029]
FIG. 2 is a block diagram showing a configuration of variable gain amplifier 200 according to the
present embodiment. Variable gain amplifier 200 includes attenuator 100, amplifier 30 and time
constant circuit 32. The variable gain amplifier 200 is integrally integrated on one
semiconductor substrate. The attenuator 100 attenuates the input signal Vin and outputs the
first output signal Vx1 and the second output signal Vx2 to the amplifier 30 that amplifies the
signals applied to the two input terminals. Although described later in detail, the amplifier 30 has
two input terminals, and includes two amplification units that respectively amplify the first
output signal Vx1 and the second output signal Vx2 applied to each input terminal. The amplifier
30 is capable of continuously switching which amplification unit is to be active.
[0030]
The attenuator 100 includes an input terminal 102, a volume control terminal 104, a first output
terminal 106, and a second output terminal 108 as input / output terminals. An input signal Vin
to be attenuated is input to the input terminal 102. This input signal Vin corresponds to the
analog signal SIG2 output from the D / A converter 210 of FIG. The volume control signal VOL
output from the microcomputer 230 of FIG. 1 is input to the volume control terminal 104. The
attenuator 100 switches the attenuation factor based on the volume control signal VOL,
attenuates the input signal Vin, and outputs it to the amplifier 30. The first output terminal 106
is a terminal for outputting the first output signal Vx1 to one input terminal of the subsequent
stage amplifier 30, and the second output terminal 108 is a second output signal at the other
input terminal of the amplifier 30. It is a terminal for outputting Vx2.
[0031]
The attenuator 100 includes a resistor group 10, a switch group 12, a decoder circuit 14, an up /
down counter 16, a comparison determination circuit 18, and a register circuit 20. The resistor
group 10 includes a plurality of resistors R1 to Rn connected in series, an input signal Vin is
applied to one end, and the other end is grounded. The resistance group 10 functions as a
resistance voltage dividing circuit, and a voltage obtained by dividing the input signal Vin
appears at each connection node N1 to Nn of the plurality of resistances R1 to Rn. Each
connection node N1 to Nn of the resistor group 10 is connected to the switch group 12.
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[0032]
FIG. 3 is a diagram showing an internal configuration of the switch group 12. The switch group
12 includes a plurality of switches SW1a, SW3a, SW5a, ..., SWna collectively referred to as a first
switch group SWa, and a plurality of switches SW2b, SW4b, SW6b, ..., SW collectively referred to
as a second switch group SWb. n-1) b is included. The switches in the first switch group SWa are
provided between the first output terminal 106 and the connection nodes N1 to Nn. The switches
in the second switch group SWb are provided between the second output terminal 108 and the
connection nodes N1 to Nn. The plurality of switches respectively included in the first switch
group SWa and the second switch group SWb are alternately connected to connection nodes N1
to Nn of the plurality of resistors R1 to Rn. That is, the first output terminal 106 is connected to
any of the odd-numbered connection nodes, and the second output terminal 108 is connected to
any of the even-numbered connection nodes.
[0033]
Return to FIG. The volume control signal VOL output from the microcomputer 230 and input to
the volume control terminal 104 is written to the register circuit 20. The comparison and
determination circuit 18 is connected to the register circuit 20, and reads out the volume control
signal VOL written in the register circuit 20 as digital data Dx. The digital data Dx is data serving
as a target value of the attenuation rate of the attenuator 100. Further, digital data Dy
corresponding to the present attenuation factor is input to the comparison determination circuit
18. The comparison / determination circuit 18 compares the digital data Dx and Dy, and outputs
an up signal to the up / down counter 16 when Dx> Dy, a down signal when Dx <Dy, and a stop
signal when Dx = Dy.
[0034]
The up / down counter 16 increases / decreases the digital data Dy based on the up signal and
the down signal output from the comparison / determination circuit 18. That is, when the up
signal is input, the digital data Dy is increased by one, and when the down signal is input, the
digital data is decreased by one. The digital data Dy output to the switch group 12 approaches
the digital data Dx, which is the target value, by the up / down counter 16 and the comparison
determination circuit 18.
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[0035]
The decoder circuit 14 selects one of the first and second switch groups SWa and SWb
corresponding to the digital data Dy output from the up / down counter 16 one by one and turns
it on. The decoder circuit 14 may associate, for example, the digital data Dy with the connection
node N. That is, when the digital data Dy = i is an odd number, in the first switch group SWa, the
i-th switch SWia is turned on and the other switches are turned off, and in the switch of the
second switch group, the connection state of the switches is Hold. When the digital data Dy = i is
an even number, the i-th switch SWib is turned on in the second switch group, the other switches
are turned off, and the connection state of the first switch group SWa is held.
[0036]
Since the digital data Dy is continuously changed by the up / down counter 16, two adjacent
switches belonging to the first and second switch groups are simultaneously turned on. As a
result, the first output signal Vx1 and the second output signal Vx2 respectively appearing at the
first output terminal 106 and the second output terminal 108 are attenuated at different
attenuation rates of the input signal Vin, and become signals having different amplitudes.
[0037]
The above is the configuration of the attenuator 100. Next, the configuration of the amplifier 30
will be described. FIG. 4 is a circuit diagram showing the amplifier 30 and the time constant
circuit 32. As shown in FIG. The amplifier 30 is a voltage follower circuit using an operational
amplifier OP1 having two differential input terminals, and the output terminal and the inverting
input terminal of the operational amplifier OP1 are connected by a feedback path.
[0038]
FIG. 5 is a circuit diagram showing a configuration of operational amplifier OP1 used for
amplifier 30. Referring to FIG. The operational amplifier OP1 has two sets of differential input
terminals. Hereinafter, the first differential input terminal is referred to as A channel, and the
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second differential input terminal is referred to as B channel. The operational amplifier OP1
includes transistors M1 to M10 and an output amplification stage 50.
[0039]
The operational amplifier OP1 includes a transistor M1 and a transistor M2, and includes a first
differential pair 52 corresponding to the A channel, a transistor M3 and a transistor M4, and a
second differential pair 54 corresponding to the B channel. Have two differential pairs. The
transistors M1 to M4 are P-channel MOS transistors, and their gate terminals are the first
noninverting input terminal (+ A), the first inverting input terminal (-A), and the second
noninverting input terminal (+ B) , And the second inverting input terminal (-B).
[0040]
The transistor M7 is connected as a tail current source to the first differential pair 52 configured
by the transistor M1 and the transistor M2. The transistor M7 is current-mirror connected to the
transistor M8. The transistors M7 and M8 are P-channel MOS transistors, and the drain terminal
of the transistor M8 is connected to the first current supply terminal 60. Similarly, a transistor
M9 is connected to a second differential pair 54 configured of the transistor M3 and the
transistor M4. The transistor M9 is current-mirror connected to the transistor M10. The drain
terminal of the transistor M10 is connected to the second current supply terminal 62. The first
current supply terminal 60 and the second current supply terminal 62 are connected to the time
constant circuit 32. The time constant circuit 32 generates a first bias current Ibias1 and a
second bias current Ibias2 that increase and decrease in a complementary manner according to
the time constant. As a result, in the first differential pair 52, a first bias current Ibias1 flows as a
tail current, and in the second differential pair 54, a second bias current Ibias2 flows as a tail
current.
[0041]
The transistor M 5 and the transistor M 6 are current mirror loads connected in common to the
first differential pair 52 and the second differential pair 54. The transistor M5 and the transistor
M6 are N channel MOS transistors, the source terminal is grounded, and the gate terminal is
connected to the drain terminal of the transistor M5. The drain terminal of the transistor M5 is
connected to the drain terminals of the transistor M1 and the transistor M3. Similarly, the drain
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terminal of the transistor M6 is connected to the drain terminals of the transistor M2 and the
transistor M4. The transistor M5 and the transistor M6 function as constant current loads of the
first differential pair 52 and the second differential pair 54.
[0042]
The output amplification stage 50 is connected to the drain terminal of the transistor M6. The
output amplification stage 50 amplifies the output current Iout generated by the two differential
pairs and outputs the amplified output current from the output terminal 64. The output
amplification stage 50 may be configured to include an output stage of a general operational
amplifier, that is, an amplification stage and a buffer, and the circuit type is not particularly
limited in the present embodiment.
[0043]
The operation of the operational amplifier OP1 configured as described above will be described.
The mutual conductance gm1 of the first differential pair 52 is given by gm1 = 1 (β × Ibias1).
Here, β is given by β = W / L × μCox using the gate width W, the gate length L, the mobility
μ, and the capacitance Cox of the gate oxide film. Now, assuming that the difference between the
voltages input to the first non-inverting input terminal (+ A) and the first inverting input terminal
(-A), that is, the differential input voltage is Vin1, the differential generated by the first
differential pair The current Iout1 is Iout1 = gm1 × Vin1. Similarly, when the transconductance
gm2 of the second differential pair 54 is given by gm2 = × (β × Ibias2), and the differential
input voltage is Vin2, the differential current Iout2 generated by the second differential pair 54
Becomes Iout2 = gm2 × Vin2.
[0044]
The output current Iout amplified by the output amplification stage 50 is given by the sum of
differential currents Iout1 and Iout2 generated by the first differential pair 52 and the second
differential pair 54, respectively. That is, it is given by Iout = Iout1 + Iout2 = gm1 × Vin1 + gm2
× Vin2. Thus, the transconductances gm1 and gm2 of the differential pair are given as a
function of the first bias current Ibias1 and the second bias current Ibias2, respectively.
Therefore, in this operational amplifier OP1, either A channel or B channel corresponding to the
first differential pair 52 and the second differential pair 54 is controlled by controlling the first
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bias current Ibias1 and the second bias current Ibias2. It can be switched continuously whether
to make it active.
[0045]
In the present embodiment, time constant circuit 32 controls the sum of the tail currents flowing
in first differential pair 52 and second differential pair 54 to be a constant value Iss, and
Depending on which of the tail currents supplied to the second differential pair 54 is to be
increased, which of the A channel and the B channel is dominant is adjusted. For example, when
Ibias1 = 0 and Ibias2 = Iss, voltages input to the second non-inverting input terminal (+ B) and
the second inverting input terminal (−B) are differentially amplified, and Ibias1 = Iss, Ibias2 = 0
In this case, the voltages input to the first non-inverted input terminal (+ A) and the first inverted
input terminal (-A) can be differentially amplified. When bias current is supplied to both the first
and second differential pairs, the differential input voltages of the A and B channels are amplified
in proportion to the square root of the bias current.
[0046]
Return to FIG. The first output signal Vx1 and the second output signal Vx2 of the attenuator
100 are input to the first and second non-inverting input terminals of the operational amplifier
OP1, respectively. The time constant circuit 32 increases or decreases the first bias current
Ibias1 and the second bias current Ibias2 with a predetermined time constant while maintaining
a complementary relationship with each other. At this time, in the amplifier 30, it is continuously
switched which of the A channel and the B channel of the operational amplifier OP1 is made
active.
[0047]
As described above, the first output signal Vx1 and the second output signal Vx2 are signals of
different amplitudes in which the input signal Vin of the variable gain amplifier 200 is attenuated
at different attenuation rates. Therefore, when the operating state of the operational amplifier
OP1 is transitioned from the state in which the A channel is active to the state in which the B
channel is active, the amplitude of the output signal Vout is the amplitude of the first output
signal Vx1 to the amplitude of the second output signal Vx2. It will be switched smoothly.
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[0048]
The operation of variable gain amplifier 200 configured as described above will be described.
FIG. 6 is a time chart showing an operating state of variable gain amplifier 200 according to the
present embodiment. For simplicity of explanation, it is assumed that the amplitude and
frequency of the input signal Vin are constant. During the period from time T0 to T1, the switch
SW1a is on in the first switch group SWa, and the switch SW2b is on in the second switch group
SWb. The amplitudes of the first output signal Vx1 and the second output signal Vx2 at this time
are Vamp1 and Vamp2, respectively. The amplitude of the first output signal Vx1 is equal to the
amplitude of the input signal Vin.
[0049]
Further, the bias current generated by the time constant circuit 32 is set to Ibias1 = Iss, Ibias2 =
0, and the A channel of the operational amplifier OP1 of the amplifier 30 is active. At this time,
the amplifier 30 amplifies the first output signal Vx1 with a gain of 1 and outputs it, so the
overall gain (attenuation factor) of the variable gain amplifier 200 is 0 dB, that is, 1 ×. In this
state, the digital data Dy corresponding to the current attenuation factor output from the decoder
circuit 14 is one. In addition, the up / down counter 16 outputs a stop signal.
[0050]
At time T1, the user reduces the volume. The microcomputer 230 outputs a volume control
signal VOL corresponding to the volume after change to the variable gain amplifier 200. The
volume control signal VOL is written to the register circuit 20. In FIG. 6, the case where the
digital data Dx corresponding to the volume after the change is 6 will be described. When the
data in the register circuit 20 is rewritten, the comparison / determination circuit 18 compares
the digital data Dx and Dy. In this state, since Dy <Dx, the comparison / determination circuit 18
outputs an up signal, and the up / down counter 16 sets the digital data Dy to 2. The decoder
circuit 14 turns on the switch SW2b of the second switch group SWb when the digital data Dy =
2 is input. However, in the example shown in FIG. 6, there is no change since the switch SW2b is
turned on in advance before time T1.
[0051]
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The up / down counter 16 outputs the synchronization signal SYNC to the time constant circuit
32 at the same time as outputting the up signal to the decoder circuit 14. When the
synchronization signal SYNC is input, the time constant circuit 32 decreases the bias current
Ibias1 according to the time constant and increases the bias current Ibias2. As the bias current
changes, the active channel of the operational amplifier OP1 switches from A to B. That is, the
amplitude of the output signal Vout of the variable gain amplifier 200 gradually changes from
the amplitude Vamp1 of the first output signal Vx1 to the amplitude Vamp2 of the second output
signal Vx2 in the transition period of the time constant circuit 32 from time T0 to T1. Do.
[0052]
When Ibias2 = Iss and Ibias1 = 0 at time T2, the B channel of the operational amplifier OP1
becomes active. At time T2, the comparison and determination circuit 18 compares the digital
data Dy = 2 with the digital data Dx = 6, and outputs an up signal again. When an up signal is
output from the comparison / determination circuit 18, the up / down counter 16 increments the
digital data Dy by one to Dy = 3. When Dy = 3 is input, the decoder circuit 14 turns on the switch
SW3a of the first switch group SWb and turns off the switch SW1a. At this time, the amplitude of
the first output signal Vx1 is switched to Vamp3. Since Dy is an odd number, switching of the
second switch group SWb is not performed.
[0053]
The synchronization signal SYNC is input to the time constant circuit 32 again, and the bias
current Ibias2 is decreased according to the time constant to increase the bias current Ibias1. As
the bias current changes, the active channel of the operational amplifier OP1 switches from B to
A. That is, in the transition period of the time constant circuit 32 from time T1 to T2, the
amplitude of the output signal Vout of the variable gain amplifier 200 gradually changes from
the amplitude Vamp2 of the second output signal Vx2 to the amplitude Vamp3 of the first output
signal Vx1. Do.
[0054]
By repeating the same operation after time T3, the digital data Dy is gradually increased by the
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comparison determination circuit 18 and the up / down counter 16, the amplitude of the output
signal Vout is gradually decreased, and the volume is switched. When Dx = Dy at time T6 and a
desired volume value is obtained, the comparison / determination circuit 18 outputs a stop
signal. The up / down counter 16 stops increasing or decreasing of the digital data Dy when the
stop signal is input.
[0055]
As described above, according to the variable gain amplifier 200 according to the present
embodiment, when the volume control signal VOL after the change is designated by the
microcomputer 230, the volume of the comparison / determination circuit 18 and the up / down
counter 16 are automatically one step The desired value approaches one by one. If the up / down
counter 16 and the comparison / determination circuit 18 are not provided, it is necessary to
rewrite the register circuit 20 every time in the microcomputer 230 until the target volume value
is reached from the current volume value. It will increase. Also, if data corresponding to the
target volume value is written directly to the register circuit 20, the amplitude of the output
signal will change rapidly if the difference with the current volume value is very large, so noise
will occur. Resulting in. That is, according to variable gain amplifier 200 according to the present
embodiment, it is possible to gently switch the amplitude of the signal output from speaker SP1
to reduce the occurrence of noise and to reduce the load on microcomputer 230.
[0056]
It is understood by those skilled in the art that the above-described embodiment is an
exemplification, and that various modifications can be made to the combination of each
component and each processing process, and such modifications are also within the scope of the
present invention. is there.
[0057]
FIGS. 7A and 7B are circuit diagrams showing modified examples of the variable gain amplifier
200 of FIG.
The variable gain amplifier 200 of FIG. 7A includes an attenuator 100 and an operational
amplifier OP1. A signal Vin to be amplified by this variable gain amplifier is input to the first noninverted input terminal (+ A) and the second non-inverted input terminal (+ B) of the operational
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amplifier OP1, and the first inverted input terminal (-A), The first output terminal 106 and the
second output terminal 108 of the attenuator 100 are connected to the second inverting input
terminal (-B). The variable gain amplifier 200 configured in this manner is a non-inversion type
amplifier using the attenuator 100 of FIG. 2 as a feedback resistor, and the gain is gradually
changed by changing the value of the feedback resistor. be able to.
[0058]
The variable gain amplifier 200 of FIG. 7B also includes the attenuator 100 and the operational
amplifier OP1. In this variable gain amplifier 200, the other end of the resistor group 10 of the
attenuator 100 is connected to the output terminal of the operational amplifier OP1 instead of
being grounded. The reference voltage Vref output from the voltage source is input to the first
noninverting input terminal (+ A) and the second noninverting input terminal (+ B) of the
operational amplifier OP1. The first output terminal 106 and the second output terminal 108 of
the attenuator 100 are connected to the first inverting input terminal (-A) and the second
inverting input terminal (-B) of the operational amplifier OP1, respectively. The variable gain
amplifier 200 configured in this manner is an inverting amplifier using the attenuator 100 of FIG.
2 as a feedback resistor, and the gain is gradually changed by changing the value of the feedback
resistor. Can.
[0059]
In the embodiment, when the up signal and the down signal are input, the up / down counter 16
counts up or down the digital data Dy one by one. However, the present invention is not limited
thereto. It is also good. This step may be set in a range where noise does not occur. Also, the
counting step may be variable. The noise generated at the time of volume change depends on the
absolute value of the amount of fluctuation of the amplitude of the output signal Vout. Therefore,
for example, when the amplitude of the output signal Vout is large, the counting step is set small
and the change in the amplitude is set small. When the amplitude of the output signal Vout is
small, the counting step may be set large. In this case, it is possible to shorten the time until
transition to a desired volume value while suppressing the occurrence of noise.
[0060]
Here, since the amplitude of the output signal Vout depends on the attenuation factor of the
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attenuator 100 and the amplitude of the input signal Vin, the counting step of the up / down
counter 16 may be switched according to either. When changing the count step according to the
attenuation factor of the attenuator 100, the digital data Dy is one step in the range of Dy1 to
Dy2, two steps in the range of Dy2 to Dy3, and four steps in the range of Dy3 to Dy4. Settings
such as can be considered.
[0061]
Also, the amplifier 30 shown in FIG. 4 and FIGS. 7A and 7B may have three or more differential
input terminals. For example, when three differential input terminals are provided, the
operational amplifier OP1 of FIG. 5 is provided with three differential pairs, and the time
constant circuit 32 generates three bias currents Ibias1 to Ibias3 for each differential pair. Just
do it. The attenuator 100 shown in FIGS. 2 and 3 may be provided with the first to third output
terminals, and the first to third switch groups may be provided for each of the output terminals.
Similarly, more differential input pairs may be provided.
[0062]
In the embodiment, the switches included in the first switch group SWa and the second switch
group SWb are described as being alternately connected to the connection node of the resistor
group 10. However, the present invention is not limited thereto. In the case where there is a
switch, switches included in each of the first switch group SWa and the second switch group
SWb may be provided in all connection nodes.
[0063]
FIG. 1 is a block diagram showing a configuration of an audio signal output device in which a
variable gain amplifier according to an embodiment is used.
It is a block diagram which shows the structure of the variable gain amplifier of FIG. It is a figure
which shows the internal structure of the switch group of FIG. FIG. 3 is a circuit diagram showing
an amplifier and a time constant circuit of FIG. It is a circuit diagram which shows the structure
of the operational amplifier used for the amplifier of FIG. It is a time chart which shows the
operation state of the variable gain amplifier of FIG. FIGS. 7A and 7B are circuit diagrams
showing modifications of the variable gain amplifier of FIG.
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Explanation of sign
[0064]
100 attenuator, 10 resistance group, 12 switch group, 14 decoder circuit, 16 up / down counter,
18 comparison / determination circuit, 20 register circuit, 102 input terminal, 104 volume
control terminal, 106 first output terminal, 108 second output terminal , 30 amplifiers, 32 time
constant circuits, 200 variable gain amplifiers, SWa first switch group, SWb second switch group,
Vx1 first output signal, Vx2 second output signal, OP1 operational amplifier, 202 power
amplifier, 210 D / A Converter, 220 playback devices, SP1 speakers, 230 microcomputers.
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