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DESCRIPTION JP2007243992

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DESCRIPTION JP2007243992
A circuit and system for ramping a voltage across a load (506). A charging circuit (500) for
charging a capacitor (501) to generate a ramp up waveform. The circuit (511) selectively
disconnects the first driver (510) from the load (506) during ramp up mode, and the load (506)
and the first driver (510) during the normal operating mode. Combine The ramp up driver (507a)
selects the load (506) during ramp up mode to ramp up the voltage across the load (506) in
response to the ramp up waveform generated by the charging circuit (500). Join together. The
discharge circuit (503d, 514a, b) discharges the capacitor (501) to generate a power down
waveform. The circuit (511) selectively disconnects the first driver (501) from the output load
(506) during a ramp down of the voltage across the output load (506). [Selected figure] Figure
5C.
Circuit and system for controlling transient response during power up and down of voice device
[0001]
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates
generally to electronic circuits, and more particularly to circuits and methods for controlling
transient response during power up and power down of audio devices, and It relates to the
system to use.
[0002]
Description of Related Art: Purchasers of modern home audio systems and portable audio
systems expect improved audio performance such as more options to control playback from a
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given recording media Do.
One of the most important performance criteria is the removal of clicks, pops, noise and other
artifacts that are audible to the user. These audible artifacts not only distract the listener but can
damage the speaker system or the headset system. This is especially true for transient response
artifacts such as clicks and pops. Clicks and pops can spike the output signal driving the speaker
and headset to a relatively high level.
[0003]
In a typical audio system, a load (eg, a speaker or headset) is AC coupled to an audio integrated
circuit that provides an electrical analog audio signal via a coupling capacitor. The normal steady
state output node voltage is approximately one half of the power supply voltage. However, before
power is applied to the circuit, the output node voltage at the coupling capacitor is zero volts.
Subsequently, as the circuit powers up, the output node voltage transitions from zero volts to a
steady state voltage, thereby charging the coupling capacitor. This voltage transition may
produce an audible sound, commonly referred to as "pop", to the speaker or headset. "Pop" can
also occur when the system power is down and when the output node transitions from steady
state voltage to zero volts.
[0004]
Currently, there are several different techniques in the art for controlling pop, and these
techniques adversely affect other aspects of system performance. Thus, other aspects of system
performance require new circuits and methods to control pops without significant impact.
[0005]
SUMMARY OF THE INVENTION According to one embodiment of the inventive concept, a circuit
for ramping a voltage across a load is disclosed. The charging circuit charges the capacitor to
generate a ramp up waveform. The circuit also includes selectively disconnecting the first driver
from the load during ramp up mode and coupling the load and the first driver during the normal
operating mode. A ramp up driver is selectively coupled to the load during ramp up mode to
ramp up the voltage across the load in response to a ramp up waveform generated by the
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charging circuit.
[0006]
The principles of the present invention are also provided for ramping down the voltage across
the output load. The capacitor is precharged to a selected voltage, and a discharge circuit
discharges the capacitor to generate a ramp down waveform. The circuit is also provided to
selectively disconnect the first driver from the output load while ramping down the voltage
across the output load. The ramp down driver selectively ramps down the voltage across the
output load in response to the ramp down waveform generated by the discharge circuit.
[0007]
The inventive concept allows transient response control to appear on the output load while the
device is powering up and down. These concepts are particularly useful for (but not necessarily
limited to) voice applications to eliminate or minimize audible "pops" in voice systems.
[0008]
For a more complete understanding of the present invention and its advantages, reference should
be made to the following description in connection with the accompanying drawings.
[0009]
DESCRIPTION OF THE PREFERRED EMBODIMENTS The principles of the present invention and
their advantages are best understood by referring to the embodiments shown in FIGS. 1-5, and
like numbers in these figures refer to like parts. There is.
[0010]
FIG. 1 is a diagram of a general audio system 100, such as a portable compact disc player, in
accordance with the principles of the present invention.
The digital media drive 102 plays digital data from the storage media, such as 1 bit or multibit
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encoded voice, and transmits the data to the DAC subsystem 101 along clock and control signals.
Do.
The storage medium may be a compact disc (CD) or a fixed medium such as RAM or a readable /
writable memory such as a flash memory for storing audio formatted in MPEG3. The resulting
analog (voice) data is subjected to further processing in circuit block 103 prior to amplification
of amplifier block 104. The amplifier block 104 then drives a set of conventional speakers 105,
headsets or the like. The audio processing circuit and DAC of block 103 may be integrated into a
single integrated circuit or may include multiple integrated circuits. Furthermore, in the case of
external speakers, this integrated circuit generally includes a line driver for driving the
connection to the audio amplifier, which also acts as an amplifier for directly driving the headset.
[0011]
FIG. 2A shows the first possible technique for eliminating pops in the output. Here, the external
load is represented by the resistor 202 connected to the amplifier 203 by the coupling capacitor
201 driven by the on-chip amplifier (driver) 203 via the node 204a. The external shorting switch
205 is controlled by the control voltage Vc from the associated drive chip via the pad or pin
204b.
[0012]
The operation of the circuit of FIG. 2A is illustrated in the diagrams of FIGS. 2B and 2C. During
power up, while the output voltage Vout ramps up, the control signal Vc closes the shorting
switch 205 and shorts the output node to ground. After Vout ramps up to a nearly final value,
control signal Vc changes switch 205 to the open state. The system is now in normal operation.
The transient response voltage or transient response current does not pass through the load 202.
[0013]
Disadvantages in the approach of FIG. 2A include the extra cost of the extra short circuit switch
as well as the extra control node and associated control circuitry.
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[0014]
The second approach is illustrated in FIGS. 3A-3C.
In this case, the output load modeled by the resistor 302 coupled to the amplifier 300 by the
coupling capacitor 301 is driven by the integrated circuit via the single node 303. The on-chip
amplifier 300 is coupled to the output pin via the on-chip resistor 304 and the internal shorting
switch 305.
[0015]
Generally, as shown in FIGS. 3B and 3C, during the start-up period, the internal short 305 is open
(the voltage Vc controlling the internal short 305 is approximately zero volts). Therefore, the
output voltage Vout ramps up slowly while charging the coupling capacitor 301 slowly via the
resistor 304. The voltage applied to the output load initially ramps up and then ramps down as
the capacitor 301 charges. The output transient response signal power in the voice band is
limited at the beginning of the charge cycle because dv / dt is large in this interval.
[0016]
The main disadvantage of the approach shown in FIG. 3A is the significant increase in start-up
time caused by slow RC charging.
[0017]
The digital pop guard is shown in FIG. 4A, where the load is represented by the resistive element
402 and the coupling capacitor element 401.
The input to drive amplifier 402 is provided by a digital to analog converter (DAC) 403 to drive
the output load via node 404. The DAC 403 ramps up the throughput of the amplifier 400
sufficiently slowly to eliminate pops. As generally shown in FIG. 4B, this technique requires a
significant amount of time, including a system initialization period to set up the DAC, and a
subsequent output voltage ramp up period. This technique is also applicable only to systems with
one or more available DACs.
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[0018]
In accordance with the principles of the present invention, an independent control circuit is used
to perform a fast start-up sequence. This independent circuit charges the output node with a
substantially linear ramp, after which the line driver or headphone amplifier is normally taken
over for system operation.
[0019]
In FIG. 5A, charging circuit 500 charges external capacitor 501 from a pair of current sources
502 a, b via node 505. The capacitance of capacitor Cext is selected as a function of the desired
rate of ramping (up or down). The charging and discharging of the capacitor Cext is controlled by
a set of switches 503a, e labeled S1 to S5 for the purpose of illustration. Resistor 504, having a
nominal resistance value, is used to maintain voltage Vref at a predetermined level during normal
operation.
[0020]
FIG. 5C shows an output circuit driving n loads 506, which may be speakers, a headset, or some
combination thereof. During the power ramping process, up driver 507a drives output load 506
via switch 508a (Sup) and switch 509 (named Sb1 to Sbn, respectively). During normal operation,
line driver / headset amplifier 510 drives the load via switch 511. Finally, during the ramp down
of power, the down driver 507b is used via switch 508b (Sdown) and switch 509.
[0021]
The operation of the charging circuit 500 and the output circuit 500 related thereto may now be
described beginning with the ramp up process. All three stages (ramp up, normal mode, ramp
down) are shown in FIGS. 6A-6G. The high level shown in FIGS. 6C-6D represents the closed state
of a given switch as controlled by an active high control signal or switch, and the low level is
controlled by a non-active low control signal. Indicates the corresponding open state.
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[0022]
During the ramp up phase, the power supply is switched on during the time to allow the supply
voltage Vdd to stabilize. Once this occurs, switches Sup and Sb1 to Sbn are closed and switches
S01 to S0n are open. In this configuration, the output load 506 is driven by the up driver 507a
from the input voltage Vref generated by the charging circuit 500. Furthermore, the output node
512 is enabled and the switch Sdown is opened.
[0023]
With respect to charging circuit 500, switches S1, S2, S4 and S5 are initially opened and switch
S3 is closed so that capacitor 501 begins to charge linearly from current source 502a. At the
same time, Vref starts to ramp up, and the up driver 507a ramps up the drive to the output load
506 linearly. The ramping process continues until Vref is approximately equal to the threshold
Vcomp, and the signal ChargeEnd is generated by the comparator circuit 513 shown in FIG. 5B.
(Here, Vcomp is a current source 515 having a current value equal to that of the resistor 516
having the resistance value Rref and the sum of I1 and I2, or the current sources 502a and 502b
operating from the supply rail. It is chosen by choosing. ) ChargeEnd transitions the output ramp
up process to a new stage. Switches S1 and S5 are closed to maintain a voltage Vref of
approximately (I1 + I2) / Rref. Furthermore, the switches Sb1 to Sbn are opened and the switches
S01 to S0n are closed. The device now has its output load 506 driven by the line driver / headset
amplifier 510 and is in its normal operating mode configuration.
[0024]
The preferred ramp down sequence is as follows. The line driver / headset amplifier 510 is
decoupled from the output load by the open switches So1-Son. Switches Sb1-Sbn are closed to
switch the output load to the up and down drivers 502a, b. The switch Sup is open and the
switch Sdown is closed to select the down driver 502b to drive the output load.
[0025]
In charging circuit 500, switches S2 and S4 are closed and switches S1, S3 and S5 are open. Load
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transistors 514a and 514b are turned on. The external capacitor 501 then begins to discharge
through transistor 502b such that Vref begins to ramp down. Next, the down driver 507b ramps
down the voltage for the output load.
[0026]
Once the transient response current is over, the power supply and its supply voltage Vdd can be
powered down.
[0027]
Thus, the principles of the present invention provide a means for fast ramping and ramping
down of the voltage driving the load.
In the illustrated embodiment, the capacitor is charged and discharged to generate a linear
waveform. One set of individual buffers, responsive to this waveform, ramps up or down the
voltage to the output load without popping. Once the ramp up is complete, the conventional line
driver / headphone amplifier receives control of the output. In ramp down, the power supply
voltage can be turned off after the transient current stops, thereby eliminating pops during the
power down process.
[0028]
Although the present invention has been described with reference to particular embodiments,
these descriptions are not intended to be construed in a limiting sense. Various modifications of
the disclosed embodiments of the invention, as well as alternative embodiments of the invention,
will be apparent to persons skilled in the art upon reference to the description of the invention. It
should be understood by those skilled in the art that the disclosed concepts and specific
embodiments can be readily used as a basis for modifying or designing other structures to carry
out the same purpose of the present invention. is there. Furthermore, it should be understood by
those skilled in the art that equivalent constructions do not depart from the spirit and scope of
the present invention as set forth in the above claims.
[0029]
Accordingly, the claims are intended to cover any modifications or embodiments that fall within
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the true scope of the present invention.
[0030]
FIG. 1 is a diagram of a general audio system, such as a portable compact disc player, in
accordance with the principles of the present invention.
FIG. 2A shows the first possible technique for eliminating pops in the output. FIG. 2B illustrates
the operation of the circuit of FIG. 2A. FIG. 2C also illustrates the operation of the circuit of FIG.
2A. FIG. 3A shows a second approach in which the output load modeled by the capacitor and the
resistor is driven from the integrated circuit via a single node. FIG. 3B shows a second approach
in which the output load modeled by the capacitor and the resistor is driven from the integrated
circuit through a single node. FIG. 3C shows a second approach in which the output load
modeled by the capacitor and the resistor is driven from the integrated circuit through a single
node. FIG. 4A shows a digital pop guard. FIG. 4B illustrates a technique that requires a significant
amount of time, including an initialization period to set up the DAC and a subsequent ramp up
period of the output voltage. FIG. 5A shows a charging circuit that charges external capacitors
from a pair of current sources through nodes. FIG. 5B shows an exemplary comparator circuit for
generating an end of charge signal to the external capacitor. FIG. 5C shows an output circuit that
drives n loads, which may be speakers, a headset, or some combination thereof. FIG. 6A is a
diagram illustrating the operation of the circuit of FIGS. 5A-5C during ramp up, normal operating
and ramp down modes. FIG. 6A is a diagram illustrating the operation of the circuit of FIGS. 5A5C during ramp up, normal operating and ramp down modes. FIG. 6A is a diagram illustrating the
operation of the circuit of FIGS. 5A-5C during ramp up, normal operating and ramp down modes.
FIG. 6A is a diagram illustrating the operation of the circuit of FIGS. 5A-5C during ramp up,
normal operating and ramp down modes. FIG. 6A is a diagram illustrating the operation of the
circuit of FIGS. 5A-5C during ramp up, normal operating and ramp down modes. FIG. 6A is a
diagram illustrating the operation of the circuit of FIGS. 5A-5C during ramp up, normal operating
and ramp down modes. FIG. 6A is a diagram illustrating the operation of the circuit of FIGS. 5A5C during ramp up, normal operating and ramp down modes.
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