close

Вход

Забыли?

вход по аккаунту

?

DESCRIPTION JP2008252169

код для вставкиСкачать
Patent Translate
Powered by EPO and Google
Notice
This translation is machine-generated. It cannot be guaranteed that it is intelligible, accurate,
complete, reliable or fit for specific purposes. Critical decisions, such as commercially relevant or
financial decisions, should not be based on machine-translation output.
DESCRIPTION JP2008252169
PROBLEM TO BE SOLVED: To switch from an operation system to a standby system without
interruption of an acoustic signal. SOLUTION: A "node 1" and a "node 2", a "node 3" and a "node
4" are dualized into an active system and a standby system. The same acoustic signal is set to be
input to the active and standby nodes, and the same signal processing parameter is set to the
active and standby nodes, respectively. The acoustic signal is subjected to the same signal
processing. Then, the acoustic signal of the signal processing result is sent out to the A bus 26 in
a frame allocated from the operation system node, and the transmission from the standby system
node is prohibited. When the switching instruction is generated, transmission of the frame is
stopped from the active node, transmission of the frame is started from the standby node, and
this process is performed in the same sampling cycle. [Selected figure] Figure 1
Acoustic signal processor
[0001]
The present invention relates to an acoustic signal processing apparatus in which acoustic
signals are transmitted and received via a bus between a plurality of nodes connected to a bus
for acoustic signal transmission.
[0002]
FIG. 17 shows an example of a conventional tone synthesizing apparatus in which acoustic
signals are transmitted and received via a bus between a plurality of nodes connected to a bus
for transmitting an acoustic signal.
10-04-2019
1
In the musical tone synthesizing apparatus shown in FIG. 17, a MIDI I / O (Input / Output) unit
202 inputs and outputs MIDI signals to and from an external MIDI device. For example, a MIDI
keyboard and other MIDI performance operations MIDI performance information from the child
is input via the MIDI I / O unit 202. The other I / O (Input / Output) unit 204 performs input /
output of various signals other than MIDI signals, and the panel switch unit 206 is used as
various tone color setting operators operated by the user. . The sound source unit 250 includes
sound source LSIs 252 and 254 to synthesize tone signals. The display 208 displays various
information to the user, such as the setting state of the sound source unit 250. The external
storage device 210 is configured of a hard disk or the like. The CPU 212 controls each part of the
tone synthesizing system via the CPU bus 218 by executing a control program. The ROM 214
stores a control program of the CPU 212 and the like. The RAM 216 is used as a work memory of
the CPU 212.
[0003]
The sound source LSIs 252 and 254 that constitute the sound source unit 250 generate
waveform data based on the performance information and the sound generation parameters
supplied via the CPU bus 218, and based on the effect parameters supplied similarly. And effect
processing is applied to the waveform data. The expansion boards 256, 258, 260 in the sound
source unit 250 can perform various processes such as waveform data combining processing,
effect processing, recording processing, etc. according to the type of expansion board, and
together with the sound source LSIs 252, 254, the sound source unit 250. To realize the
predetermined function. A bus for waveform data transfer (hereinafter referred to as "A bus")
262 is a bus capable of transmitting waveform data between the sound source LSIs 252 and 254
and the expansion boards 256, 258 and 260. Since only waveform data to which information
such as a transmission destination address is not attached is transmitted to the A bus 262, the
transmission band of the waveform data can be widened.
[0004]
Since the amount of waveform data to be transferred is large between the sound source LSIs 252
and 254, part of the waveform data is transmitted via a direct connection line directly connected
to each other. The DA converter 264 converts waveform data for two channels of the output
channel of the sound source LSI 252 into an analog signal, and the converted analog signal for
two channels is emitted from the sound system 220. The word clock generator 251 generates a
10-04-2019
2
word clock WCK which rises every sampling period. The word clock WCK is supplied to each unit
in the sound source unit 250. The word clock external input terminal 268 is a terminal provided
to receive the word clock WCK from the outside instead of the word clock WCK generated by the
word clock generator 251, and in the case of synchronizing the sampling cycle with an external
device Used for Further, the expansion boards 256, 258, and 260 are configured to be attachable
to and detachable from the sound source unit 250.
[0005]
The sound source LSIs 252 and 254 that input and output waveform data via the A bus 262 and
the expansion boards 256, 258, and 260 constitute nodes, and the configured nodes are referred
to as node A, node B, and node C. At these nodes, the data signal ADAT, the direction signal ADIR,
and the clock signal ACLK are input to and output from the A bus 262. The input / output
terminal of each of these signals is connected to the A bus 262 in a wired OR form, and at the
timing when any one node outputs the signal to the A bus 262, the input / output terminals of
the other nodes Are set to the high impedance state, and the node receives the signal transmitted
to the A bus 262 as needed. The data signal ADAT is a signal such as waveform data to be
transferred between nodes, and the clock signal ACLK is a clock signal synchronized with the
data signal ADAT.
[0006]
A period in which the data signal ADAT and the clock signal ACLK should be output is set by the
CPU 212 so as not to overlap for each node, and this period is set as a “frame”. Direction
signal ADIR is set to "L" during this frame period, thereby inhibiting signal output to other nodes.
Also, at each node, a frame signal AFRM that rises earlier by one clock of the clock signal ACLK
than the direction signal ADIR rises to “H” is also output. The frame assigned to each node is
defined by "the number of frames after the word clock WCK has risen". Therefore, each node can
detect the start timing of the frame of its own node by counting how many times a frame has
occurred after the word clock WCK has risen.
[0007]
Here, as a transmission frame, a case in which the node A is allocated a frame # 2 which is a
third frame, a frame # 0 which is a first frame to a node B, and a frame # 1 which is a second
10-04-2019
3
frame FIG. 18 shows a timing chart in FIG. At time t0 shown in FIG. 18, the word clock WCK
rises, and each of the nodes A, B, and C detects the rise. At node B to which frame # 0 is assigned,
direction signal ADIR and frame signal AFRM are lowered to "L" at time t1 when a predetermined
time has elapsed from time t0, and clock signal ACLK is output and synchronized therewith.
Output data signal ADAT.
[0008]
At time t2, when data output from node B is completed, direction signal ADIR of node B is raised
to "H". The frame signal AFRM is raised to "H" one cycle before the clock signal ACLK before time
t2, and the node C detects that the next frame is the frame # 1 assigned to the own node.
Therefore, at time t3 when a predetermined margin time has passed after the direction signal
ADIR rises, the node C operates in the same manner as the node B described above. That is, the
direction signal ADIR of the node C and the frame signal AFRM are lowered to "L" to output the
clock signal ACLK and, in synchronization with this, the data signal ADAT. A margin time between
frames is provided to avoid data collision. Next, when the frame signal AFRM of the node C is
raised to "H", the node A detects that the next frame is the frame # 2 assigned to the own node.
Then, after time signal ADIR of node C rises to "H" at time t4, the same output process as
described above is executed at node A at time t5 when a predetermined margin time has passed.
JP 2004-102131 A
[0009]
When a problem occurs in the operation of any expansion board due to deterioration of parts
constituting the expansion board, a contact failure or the like in the sound signal processing
apparatus such as a conventional tone synthesizer, signal processing on the expansion board Can
not Therefore, it is necessary to replace the expansion board having a problem, but in order to
replace the expansion board, the system has to be temporarily stopped and then replaced,
resulting in the problem that the acoustic signal is stopped. . By the way, there is a redundant
system in which an active system device that actually performs processing and a standby system
device that backs up the process are prepared, and the standby system device takes over its
operation if there is a problem with the active system device. Although it is known, in the case of
an audio signal processing apparatus, it is desired to cope with an audio signal output in a
sampling cycle without interruption, and the technique in other fields can not be applied as it is.
was there.
10-04-2019
4
[0010]
Therefore, an object of the present invention is to provide an acoustic signal processing
apparatus capable of executing switching from an operation system to a standby system without
interruption of an acoustic signal.
[0011]
In order to achieve the above object, according to the acoustic signal processing device of the
present invention, a plurality of nodes include redundant nodes in the active node and the
standby node, and the active and standby nodes are included in the nodes. The same acoustic
signal is input to each other, and the same control signal is supplied to perform the same signal
processing according to the same control signal on the same input acoustic signal. Transmission
of the signal-processed output to the audio bus by the predetermined frame is permitted only for
the active node, and transmission of the predetermined frame from the standby node is
prohibited, and when the switching instruction is issued, In the same sampling period,
transmission of a predetermined frame from the active node to the audio bus is stopped, and to
the audio bus of the predetermined frame from the standby node It is the most important feature
that the delivery is initiated.
[0012]
According to the present invention, the plurality of nodes include nodes duplicated in the active
node and the standby node, and the same acoustic signal is input to the active node and the
standby node. The same control signal is supplied, and the same signal processing is applied to
the same input acoustic signal according to the same control signal, and an audio bus with a
predetermined frame of the signal processed output Transmission to the active node is permitted
only, and transmission of the predetermined frame from the standby node is prohibited. When
the switching instruction is issued, the active node is issued within the same sampling period.
The transmission of the predetermined frame to the audio bus is stopped, and the transmission
of the predetermined frame from the standby node to the audio bus is started. Switching from de
to a node of the standby system will be able to run without the acoustic signal is interrupted.
[0013]
A block diagram showing a configuration of an acoustic signal processing apparatus according to
an embodiment of the present invention is shown in FIG.
In an acoustic signal processing apparatus 1 according to the present invention shown in FIG. 1,
10-04-2019
5
a CPU (Central Processing Unit) 10 controls the overall operation of the acoustic signal
processing apparatus 1 and controls acoustic signal processing performed by the acoustic signal
processing unit 20. It is carried out.
The flash memory 11 stores operation software and the like related to audio signal processing
performed by the audio signal processing unit 20 under the control of the CPU 10.
Since the flash memory 11 is rewritable, the operation software can be rewritten, and the version
upgrade of the operation software can be easily performed. In the RAM (Random Access
Memory) 12, a work area of the CPU 10 and a storage area such as various data are set. The
external storage device 13 is a large-capacity storage device such as a hard disk storage device,
and stores operation software, parameters, and the like. The display 14 is provided with a display
means such as liquid crystal, and displays various setting screens for the acoustic signal
processing and a screen for displaying the setting contents on the display means.
[0014]
The panel switch unit (panel SW) 15 is a variety of operators operated by the user provided on
the panel of the audio signal processing apparatus 1. The other I / O (Input / Output) unit 16 is
an input / output unit that inputs / outputs various signals other than MIDI signals. The MIDI I /
O (Input / Output) unit 17 is an input / output unit that inputs / outputs MIDI signals between an
external MIDI device and the audio signal processing apparatus 1; MIDI performance information
from the controller is input via the MIDI I / O unit 17. The microphone and sound system 18
includes a microphone that picks up an acoustic signal input to the acoustic signal processing
device 1 and a sound system that emits an acoustic signal processed by the acoustic signal
processing device 1. The CPU bus 19 is a bus through which each unit of the audio signal
processing apparatus 1 exchanges various data with each other. The CPU 10 executes each
control program to thereby execute each unit of the audio signal processing apparatus 1 via the
CPU bus 19. I have control.
[0015]
The audio signal processing unit 20 is an audio signal processing unit that performs audio
processing on an audio signal input from the microphone and sound system 18 or an analog
input card described later at each sampling period, and transmits an audio signal (Hereinafter
10-04-2019
6
referred to as "A bus") 26 is provided. Since only an acoustic signal to which information such as
a transmission destination address is not transmitted is transmitted to the A bus 26, the
transmission band of the acoustic signal can be widened, and for example, acoustic signals of
512 channels can be transmitted. The acoustic signal processing unit 20 includes eight nodes
“node 0” to “node 7” which are nodes for inputting an acoustic signal and nodes for
processing an acoustic signal and nodes for outputting a processed acoustic signal. . However,
the number of nodes can be designed to any number of nodes in the design stage. The word
clock generator 28 is an oscillator such as PLL (Phase Locked Loop), and generates a word clock
WCK which rises every sampling period. The word clock WCK is supplied to each unit in the
acoustic signal processing unit 20, and eight nodes "node 0" to "node 7" operate based on the
same sampling frequency. In this case, the word clock WCK having a sampling cycle may be
externally supplied to the clock terminal CL of the audio signal processing unit 20 to synchronize
the word clock generator 28 with the external word clock WCK. In this way, the sampling cycle
of the external device and the acoustic signal processing device 1 can be synchronized.
[0016]
“Node 0” is an analog input / output node 21 between the microphone and sound system 18,
and for example, an analog input for inputting an audio signal of 24 channels from the
microphone and sound system 18, and a processed audio signal as microphone and sound And
12 analog outputs for output to the system 18. Note that "node 0" is fixed without a removable
card. "Node 1" is a card I / O provided between the removable analog input card 22a and the
analog input card 22a and the A bus 26 and between the CPU bus 19 and controlling the input
and output of the analog input card 22a. (Input / Output) (1). The number of channels of the
analog input for inputting the acoustic signal of the analog input card 22a is, for example, 32
channels. "Node 2" is a card I / O provided between the removable analog input card 22b and the
analog input card 22b and the A bus 26 and between the CPU bus 19 and controlling the input
and output of the analog input card 22b. And (2). The number of channels of analog input for
inputting the acoustic signal of the analog input card 22b is, for example, 32 channels.
[0017]
In this way, "node 1" and "node 2" have the same configuration and are made to be nodes of the
same function, for example, "node 1" becomes the active system and "node 2" becomes the
standby system and duplicated. ing. The same control signal is supplied from the CPU bus 19 to
the “node 1” of the operating system and the “node 2” of the standby system, and the same
acoustic signal is supplied to the same input channel to each node, and the same control signal is
10-04-2019
7
generated. Corresponding to each other, the same signal processing is performed. Then, although
the output to the A bus 26 of the acoustic signal subjected to signal processing from the “node
1” of the operation system is permitted, the output to the A bus 26 from the “node 2” of the
standby system is prohibited. There is. In addition, when a switching instruction to switch
between the active system and the standby system is instructed by the user or the like, the active
system node is switched to the “node 2”, and the “node 1” is switched to the standby
system. In this case, when the switching instruction is issued, switching between the active node
and the standby node is performed within the same sampling period, so the acoustic signal is
interrupted from the switching from the active node to the standby node. It will be possible to
execute without. The switching instruction is generated when the user performs a switching
operation in the panel switch unit 15 or when an abnormality is detected in the operation of the
active node.
[0018]
Further, in the case where the active node and the standby node are duplicated, it is possible to
hot-swap the card constituting the node. As a result, since it is possible to switch to the standby
system the node composed of the card to be replaced even during the operation of the acoustic
signal processing apparatus 1, the node of the card showing signs of abnormality in the
operation is switched to the standby system and in advance. You will be able to exchange cards.
Also in this case, it is possible to switch nodes and exchange cards without interruption of the
acoustic signal.
[0019]
Next, “node 3” is provided between a DSP card 23a on which a DSP (Digital Signal Processor)
is mounted, and the DSP card 23a and the A bus 26 to control card I / O (input / output of DSP
card 23a) 3) and. Also, "node 4" is a card I / O provided between the DSP card 23b on which the
DSP is mounted and the DSP card 23b and the A bus 26 and between the CPU bus 19 and
controlling the input and output of the DSP card 23b. It consists of (4). “Node 3” and “Node
4” are loaded with the same program via the CPU bus 19 and supplied with the same control
parameters, and are regarded as nodes of the same function. For example, “Node 3” is an
active system “Node 4” is made a standby system and is duplexed. The same acoustic signal is
transferred to each node of the operating system "node 3" and the standby system "node 4" via
the A bus 26 on the same input channel, and mutually according to the same program and the
same control parameters. The same signal processing is applied to the acoustic signal. This signal
processing is, for example, processing related to mixing processing. For example, the number of
10-04-2019
8
input channels to which acoustic signals at "node 3" and "node 4" are input is 48 channels, and
the number of output channels for outputting processed acoustic signals is 24 channels. Then,
although the output to the A bus 26 of the acoustic signal subjected to signal processing from the
“node 3” of the active system is permitted, the output to the A bus 26 from the “node 4” of
the standby system is prohibited. . The switching between the active node and the standby node
is performed in the same manner as the “node 1” and “node 2” described above, and the
acoustic signal does not interrupt the switching from the active node to the standby node. Will be
able to run.
[0020]
“Node 5” is a card I / O (5) provided between the DSP card 23c on which the DSP is mounted
and the DSP card 23c and the A bus 26 and between the CPU bus 19 and controlling the input
and output of the DSP card 23c. And consists of. “Node 5” is loaded with a program and
supplied control parameters via the CPU bus 19. For example, acoustic signals of the 48 channels
are transferred via the A bus 26 and loaded. Signal processing according to the program and
control signal is applied to the acoustic signal. This signal processing is, for example, processing
related to mixing processing. The number of output channels for outputting the processed audio
signal of “node 5” is, for example, 24 channels. “Node 7” is a card which is provided
between the removable digital I / O card 24 and the digital I / O card 24 and the A bus 26 and
between the CPU bus 19 and controls the I / O of the digital I / O card 24 It is composed of I / O
(7). A control signal is supplied from the CPU bus 19 to the “node 7”. For example, acoustic
signals of the number of channels of 24 channels are transferred via the A bus 26 and subjected
to signal processing according to the control signal. It is output to 26. The number of output
channels is, eg, 64 channels.
[0021]
Also, “node 6” is a vacant node where no card is mounted, and card I is provided between the
mountable card and A bus 26 and between CPU bus 19 to control card input / output. It has only
/ O (6). By installing a DSP card as a card and supplying the same control parameters as the
program loaded to "node 5" to "node 6" via CPU bus 19, "node 6" It becomes the same function
as 5 ", and can perform duplexing which makes one node an active node and makes the other
node a standby node. Also, a digital input / output card is installed as a card, and the same
control signal as "node 7" is supplied to "node 6" via CPU bus 19, and an acoustic signal of the
same channel is transferred via A bus 26. By doing this, “node 6” has the same function as
“node 7”, and duplexing can be performed in which one node is an active node and the other
10-04-2019
9
node is an idle node. Note that an inter-node communication path shown by connecting broken
lines between card I / Os is provided between the nodes, and the communication path between
the active node and the standby node is provided by the inter-node communication path.
Communication of switching request instruction and switching permission can be performed.
[0022]
Next, details of the node configuration are shown in FIG. Only the configuration of one node is
shown in FIG. 2, and this node consists of a card 27 and a card I / O 25. The card 27 is composed
of a control microcomputer 27a and an audio circuit 27b, and the control microcomputer 27a
executes the program loaded on the card 27 or controls the audio circuit 27b according to the
supplied control signal. Sound processing is performed on the sound signal supplied to the card
27 at 27 b. The control microcomputer 27a includes a control register storing control
parameters of the audio circuit 27b. The audio circuit 27b processes the acoustic signal in
synchronization with the sampling clock in the acoustic signal processing unit 20. The card I / O
25 has a slot for mounting the card 27, and a control I / O 25a provided between the CPU bus 19
and the control microcomputer 27a, and an Audio I / O 25b provided between the A bus 26 and
the Audio circuit 27b. And a hot swap circuit (Hot Swap) 25c for hot plugging / unplugging the
card 27 into a slot. The control I / O 25a is an I / O for communication between the CPU 10 and
the control microcomputer 27a, and includes a control register storing control parameters of the
Audio I / O 25b. The Audio I / O 25 b has a buffer for temporarily storing the reception signal
from the A bus 26 to the card 27 and the transmission signal from the card 27 to the A bus 26,
and inputs and outputs acoustic signals between the A bus 26 and the audio circuit 27 b. I have
control.
[0023]
An operation clock is supplied from the card 27 to the card I / O 25. The card I / O performs
input / output control in synchronization with the operation clock. Then, since the operation
clock of the card 27 serves as a transfer clock to the A bus 26, the transfer circuit of the acoustic
signal between the card 27 and the card I / O 25 can be configured simply. Since the card 27 is
not directly connected to the A bus 26, the characteristics of the A bus 26 do not change
depending on whether the card 27 is attached to the slot of the card I / O 25. Further, the
transfer rate between the card 27 and the card I / O 25 can be made lower than the transfer rate
of the A bus 26, and the hot swap circuit 25c can be configured simply. The operating power is
supplied from the hot swap circuit 25c to the card 27. When the card 27 is mounted in the slot,
the power line for supplying the power to the card 27 is first connected to the card I / O 25. The
10-04-2019
10
transmission line for transmitting and receiving the signal is then connected.
[0024]
FIG. 3 shows an algorithm of mixing processing when the acoustic signal processing apparatus 1
shown in FIG. 1 is set in the mixing processing apparatus. In FIG. 3, a plurality of analog signals
input to the analog input unit 30 at the analog input / output node 21 of “node 0” are
converted into digital signals by the built-in AD converter and input to the input patch 33 .
Further, the plurality of analog signals input to the analog input card 22 a of “node 1” are
converted into digital signals by the built-in AD converter and input to the input patch 33.
Furthermore, the plurality of digital signals input to the digital input unit 32 of the digital input /
output card 24 of “node 7” are input to the input patch 33 as they are. A digital audio signal
of, for example, 24 channels is input from the analog input unit 30 to the input patch 33, and a
digital audio signal of, for example, 32 channels is input from the analog input unit 31b to the
input patch 33. For example, digital audio signals for 64 channels are input from the digital input
unit 32 to the input patch 33. The analog input unit 31b is an analog input unit of the analog
input card 22b of "node 2", and the same input as that of the analog input unit 31a is supplied
and converted to a digital signal in the same manner. A standby system analog input unit 31b for
the analog input unit 31a is redundantly provided.
[0025]
In the input patch 33, acoustic signals of a total of 120 channels input from the analog input unit
30, the analog input unit 31a (31b) and the digital input unit 32 are, for example, for each input
channel of the input channel unit 34a which is 24 channels. For example, it is possible to
selectively patch (connect) each input channel of the input channel unit 35, which is, for
example, 48 channels, and an audio signal from the input unit patched by the input patch 33 is
input to each input channel. Supplied. The input channel unit 34a is realized by the DSP card 23a
of "node 3", and the input channel unit 35 is realized by the DSP card 23c of "node 5". Further,
the input channel unit 34b is realized by the DSP card 23b of "node 4", and the same acoustic
signal as the acoustic signal patched to each input channel of the input channel unit 34a is
patched and supplied, and the same. The signal processing and duplexing are performed, and the
input channel unit 34b for the standby system with respect to the input channel unit 34a that is
the active system is used.
[0026]
10-04-2019
11
Each input channel in the input channel section 34a (34b) and the input channel section 35 is
provided with an attenuator, an equalizer, a compressor, a fader, and a send adjustment section
for adjusting the sending level to the MIX bus 36, and these input channels , The frequency
balance and the level sent to the MIX bus 36 are controlled. The mixing result of 24 channels in
which the 48 channel digital signals output from the input channel unit 35 are mixed in the MIX
bus 36 and the 24 channel digital signal sent out from the input channel unit 34 a (34 b) to the
MIX bus 36 are It is mixed and output from the MIX bus 36. The mixed output of 24 channels
output from the MIX bus 36 is output to the output channel section 37a. This makes it possible
to obtain 24 channels of mixed output mixed in 24 ways.
[0027]
The output channel unit 37a is, for example, 24 output channels, and each output channel is
provided with an attenuator, an equalizer, a compressor, and a fader, and is sent to the frequency
balance and output patch 38 in each output channel. Level is controlled. The output channel unit
37a is realized by the DSP card 23a of "node 3". Further, the output channel unit 37b is realized
by the DSP card 23b of "node 4", and the mixing result of 24 channels output from the MIX bus
36 to the output channel unit 37a is also supplied to the output channel unit 37b, As described
above, the signal processing and duplexing are performed, and the output channel unit 37b of
the standby system with respect to the output channel unit 37a which is the active system is
formed.
[0028]
The output patch 38 selectively patches (connects) any one of the 24 mixed signals from the
output channel unit 37 a (37 b) for each output port of the analog output unit 39 and the digital
output unit 40. Each output port is supplied with the signal from the channel patched by the
output patch 38. The analog output unit 39 is realized by the analog output unit at the analog
input / output node 21 of “node 0”, and the digital output unit 40 is realized by the digital
output unit at the digital input / output card 24 of “node 7”. ing. In FIG. 3, the portion
enclosed by broken line A and the portion enclosed by broken line F are realized by the function
of “node 0”, and the portion surrounded by broken line B is realized by the function of “node
1” or the function of “node 2” It is done. Further, the part surrounded by the broken line C
and the part surrounded by the broken line G are realized by the function of “node 7”, and the
part surrounded by the broken line D is realized by the function of “node 3” or the function of
10-04-2019
12
“node 4” . Furthermore, a portion surrounded by a broken line E is realized by the function of
“node 5”.
[0029]
Next, in the current memory in the RAM 12, an area for storing card I / O (0) and card I / O (1) to
(7) parameters included in "node 0", and each node are configured. The area | region which
stores the parameter for signal processing of card | curd 22a-24 to be done is created. Therefore,
FIGS. 4A and 4B show the configuration of the area for card I / O of the current memory and the
configuration of the area for the card. As areas for card I / O of the current memory, as shown in
FIG. 4A, areas of card I / O (0) to card I / O (7) are prepared. In each area, each parameter of card
I / O is stored, and in each parameter, card type, card ID, duplexing information, transmission
control information (frame number, channel), reception control information (frame number,
channel) Etc.). Note that only one of the outputs is permitted in the card I / O in the node that is
duplicated in the active system and the standby system. Further, as the area for the card of the
current memory, as shown in FIG. 4B, an area for the analog input / output node 21 constituting
"node 0" and an analog input constituting "node 1" A common area for the card 22a and the
analog input card 22b constituting the "node 2", a DSP card for the DSP card 23a constituting the
"node 3" and a DSP card constituting the "node 4" An area common to 23 b, an area for DSP card
23 c constituting “node 5”, and an area for digital input / output card 24 constituting “node
7”. In each of these areas, common signal processing parameters for controlling signal
processing are stored. As described above, since the cards which are dualized in the active
system and the standby system use the same common parameter, the area of the current
memory is made one common area.
[0030]
The A bus 26 is composed of a data signal line for transmitting an acoustic signal, a clock signal
line for transmitting a clock signal, a direction signal line and a frame signal line. The period in
which the acoustic signal and the clock signal should be output is set by the CPU 10 so as not to
overlap for each node. This period is a "frame", and during this frame period, a direction signal of
"L" level is output from the node to the direction signal line, thereby inhibiting signal output to
other nodes. In addition, a frame signal rising one clock earlier than the direction signal rising
from "L" to "H" is output to the frame signal line. The frame assigned to each node is defined by
"the number of frames after the word clock WCK has risen". Therefore, in each node, after the
word clock WCK rises, the card I / O counts the number of times of rising of the frame signal to
detect the start timing of the frame of the own node. Further, the input / output terminals
10-04-2019
13
connected to the respective signal lines in the A bus 26 of “node 0” to “node 7” are
connected by wired OR. As a result, a signal line in which no “L” signal is output from any
node is in a high impedance state (“H”), and the level of the signal line in which an “L”
signal is output from any node is “ It becomes L ". Therefore, during the frame period, the node
outputs the frame signal of “L” level to the frame signal line, thereby inhibiting the signal
output to the other nodes.
[0031]
Also, each node can receive the acoustic signal of the desired channel by controlling to receive
the acoustic signal on the data signal line at the timing of the channel in the frame in which the
acoustic signal to be received is output. As described above, the data signal output to the data
signal line is an acoustic signal such as waveform data to be exchanged between nodes. The clock
signal output to the clock signal line is a clock signal synchronized with the data signal. Here,
each frame is described as a frame # 0, a frame # 1, a frame # 2,... According to the order of
occurrence after the rise of the word clock WCK. For each node, one or more transmission
frames can be assigned within one sampling period. In this case, as the timing chart transmitted
by “node 0” to “node 7” in the acoustic signal processing unit 20, the timing chart shown in
FIG. 18 is taken as an example.
[0032]
Therefore, an example of the timing when “node 0” to “node 7” output a frame is shown in
FIG. In FIG. 5, "node 0" is the first frame, frame # 0, "node 1" is the second frame, frame # 1, and
"node 3" is the third frame, frame # 2, " The timing is assumed to be when the fourth frame,
frame # 3, is assigned to the node 5 ', and the fifth frame, frame # 4, is assigned to the' node 7 '.
In the timing chart shown in FIG. 5, when the word clock WCK rises at time t0, the rising of the
word clock WCK is detected at "node 0" to "node 7". Then, at the “node 0” to which the frame
# 0 is allocated, the direction signal and the frame signal AFRM fall to “L” at timing t1 when a
predetermined time has elapsed after the word clock WCK rises. Then, a clock signal (not shown)
is output to the clock signal line, and a frame # 0 of the data signal synchronized with the clock
signal is output to the data signal line Frame. In frame # 0, digitized acoustic signals for 24
channels are output to the A bus 26.
[0033]
10-04-2019
14
When the output of the data signal from "node 0" is completed, frame signal AFRM output from
"node 0" is raised to "H", and a direction signal not shown rises to "H" one clock later. It is raised.
As a result, the first rise of the frame signal AFRM on the A bus 26 is detected in “node 1”, and
it is detected that the next frame is the frame # 1 allocated to the own node. Therefore, at time
t2, the “node 1” lowers the direction signal not shown and the frame signal AFRM to “L”.
Then, a clock signal (not shown) is output to the clock signal line, and a frame # 1 of the data
signal synchronized with the clock signal is output to the data signal line Frame. In frame # 1,
digitized acoustic signals for 32 channels are output to the A bus 26. A margin time between
frames is provided to avoid data collision.
[0034]
Then, when the output of the data signal from “node 1” is completed, frame signal AFRM
output from “node 1” is raised to “H”, and a direction signal not shown is “H” one clock
later. Launched in As a result, the second rise of the frame signal AFRM on the A bus 26 is
detected in the “node 3”, and it is detected that the next frame is the frame # 2 allocated to the
own node. Therefore, at time t3, the “node 3” causes the direction signal not shown and the
frame signal AFRM to fall to “L”. Then, a clock signal (not shown) is output to the clock signal
line, and a frame # 2 of the data signal synchronized with the clock signal is output to the data
signal line Frame. In frame # 2, acoustic signals from the output channel units 37 a (37 b) for 24
channels are output to the A bus 26. The same operation is performed in "node 5" and "node 7",
and frame # 3 is output from node "5" to data signal line Frame from time t4, and frame "# 4" is
output from time t5 from "node 7". It is output to the data signal line Frame. In frame # 3, an
audio signal as a mixed result of 24 channels is output to A bus 26, and in frame # 4, an audio
signal input in 64 channels is output to A bus 26. When output of data signals from all assigned
frames is completed, each signal line of A bus 26 is maintained in a high impedance state until
word clock WCK rises next. Although one frame is assigned to each node in the example shown
in FIG. 5, a plurality of transmission frames may be assigned to one node within one sampling
(DAC) cycle.
[0035]
Next, an example of the number of input / output channels of “node 0” to “node 7” is shown
in FIG. In the example shown in FIG. 6, “node 0” receives an analog audio signal from the
microphone and sound system 18, converts it into a digital signal, and outputs it to the A bus 26
corresponding to the input patch 33 by frame # 0. Digital audio signals received from 12
10-04-2019
15
channels of the 24 channels of frame # 2 from the A bus 26 corresponding to the analog input
and output patch 38 are converted to analog signals and output to the microphone and sound
system 18 And 12 analog outputs. “Node 1” has 32 channels of analog input that outputs
analog acoustic signals from the analog input card 22 a and converts them into digital signals
and outputs them to the A bus 26 corresponding to the input patch 33 by frame # 1 There is.
“Node 2” inputs from the analog input card 22b the same audio signal as the audio signal
input to the analog input card 22a, converts it into a digital signal, and outputs it to the A bus 26
corresponding to the input patch 33 by frame # 1 It has 32 channels of analog input. However,
when the “node 2” is switched to the active system, the output to the A bus 26 is permitted.
[0036]
“Node 3” is an input channel for receiving a patched 24 channel digital audio signal out of a
total of 120 channels of frame # 0, frame # 1 and frame # 4 from A bus 26 corresponding to
input patch 33 , An input channel (a total of 48 input channels) for receiving the 24 channels of
the mixed sound signal output from the “node 5” to the A bus 26 according to frame # 3 and
an audio input from the 48 input channels It has 24 output channels for mixing the signals and
outputting them to the A bus 26 corresponding to the output patch 38 by frame # 2. Although
“node 4” has the same configuration as “node 3”, “node 4” is permitted to output frame #
2 to A bus 26 when it is switched to the active system. “Node 5” receives a patched 48channel digital audio signal out of a total of 120 channels of frame # 0, frame # 1 and frame # 4
from the A bus 26 corresponding to the input patch 33 and sends a MIX bus The mixed result of
24 channels mixed at 36 is output to the A bus 26 by frame # 3. “Node 7” receives a digital
audio signal from the digital input / output card 24 and outputs it to the A bus 26 corresponding
to the input patch 33 by the frame # 4 with a 64 channel digital input, and an A corresponding
to the output patch 38 And a digital output for outputting the patched 24-channel digital audio
signal of frame # 2 received from the bus 26 to a digital recorder or the like.
[0037]
Next, FIG. 7 shows a flowchart of a system setting process executed by the CPU 10 in the sound
signal processing apparatus 1, and FIG. 8 shows a display screen of the system setting displayed
on the display 14 at that time. When the power is turned on or the system is reset in the acoustic
signal processing apparatus 1, the system setting process is started, and the previous setting is
cleared in step S10, and the system setting display screen shown in FIG. 8 is displayed. The initial
settings are displayed on the display 14. In the initial setting, the node and the type of card
installed in each node are automatically detected, and the node number is displayed in the node
10-04-2019
16
column, and "analog input" "DSP" "digital input / output" in the card column of the display screen
The card type such as is displayed. The “node 0” is not displayed on the display screen
because it is not removable and is fixed and the type and the like are not changed. Further, in the
group column of the display screen, duplexing setting is performed in which nodes to be
duplexed in the active system and the standby system belong to the same group. The duplex
setting by grouping is set by the user, and in the illustrated example, "node 1" and "node 2" are
set to belong to "group 0", and "node 3" and "node 4" It is set to belong to "group 1". In this case,
even if the card is not installed in the node, the duplex setting can be performed.
[0038]
In addition, the A column of the display screen is a column in which the “*” mark is displayed
on the active node. The node to be activated is permitted to output the acoustic signal subjected
to the signal processing to the A bus 26, and the node to be deactivated is subjected to the signal
processing but the acoustic signal subjected to the signal processing to the A bus 26. Output is
prohibited. Note that one of the nodes in the group is active for the grouped nodes, and "node 1"
is active in "group 0" and "node 3" is active in "group 1". In addition, for nodes that are not
grouped, “node 5” and “node 7” are activated except for nodes in which cards are not
installed. Such system setting processing is performed in step S11 and subsequent steps of the
system setting processing.
[0039]
Therefore, when the initial setting process at step S10 is completed, at step S11, duplexing
setting is performed in which the user belongs to the same group the nodes to be duplexed to the
active system and the standby system. In this case, when the display screen shown in FIG. 8 is
set, the duplexing number is “2”. Next, in step S12, a current memory (for card) storing signal
processing parameters corresponding to the processing contents of the card in each node is
prepared. In this case, one memory area is prepared in one group for nodes that are duplexed,
and if it is set as shown on the display screen shown in FIG. 8, the current memory (card portion
shown in FIG. ) Are prepared. Then, in step S13, the program and signal processing parameters
according to the processing content are read from the current memory and loaded into the
analog input card 22a through the digital input / output card 24, and "node 0" through "node 7"
operate. It will be possible. The manufacturer of the acoustic signal processing apparatus 1 may
determine in advance nodes which are to be the active system and the standby system in the
duplex setting. For example, it may be decided to group the (i) th node and the (i + 1) th node
(where i is an odd number) as redundant nodes and set the odd number node to be the active
10-04-2019
17
node and the even number node to be the standby node. it can.
[0040]
Next, FIG. 9 shows a flowchart of the parameter value changing process executed by the CPU 10
when an operation for changing the signal processing parameter of the node stored in the
current memory is performed. When the signal processing parameter is operated by operating
the operation element such as the on / off switch of the fader or channel prepared in the panel
SW15, the parameter value change process is activated and the correspondence in the current
memory is activated in step S20. Parameter values are changed. Next, the display of the
parameters is updated in step S21. Furthermore, the control target node of the parameter
changed in step S22 is specified. In this case, in the case of duplexing, two nodes that are
duplexed are to be controlled. Further, whether the control object is a card or a card I / O is
specified from the parameter changed in step S23. Then, it is determined whether or not there is
a control target specified in step S24, and if it is determined that there is a control target, the
control target specified in the node specified in step S25 is a new parameter after change The
new parameter value is loaded to the control target so as to be controlled by the value, and the
parameter value change process is finished. In this case, the new parameter value is loaded to
two nodes which are duplexed if they are duplexed. If it is determined in step S24 that there is no
control target, error processing is performed to branch to step S26 to display that there is no
control target, etc., and the parameter value change processing ends.
[0041]
By the way, when there is a node set to be duplexed, the display 14 displays a switch screen
shown in FIG. 10 which can switch between the active system and the standby system only for
the node that is operating in duplex. In the switch screen shown in FIG. 10, the “node 0” and
the “group 0” of the “node 2” in the duplex operation are “node 3” as “input A (1)” and
“input A (2)”. "Group 1" of "Node 4" is displayed as "DSP (3)" and "DSP (4)", and the frame of "A
input (1)" and "DSP (3)" is bold It is shown that it is shown as an active system. On this switch
screen, by performing operations such as placing the cursor on the displayed node and clicking
on it, it is possible to issue a switching instruction of the group to which the node belongs, and at
this time, switching processing (of the group g A flowchart of the switching operation is shown in
FIG. When switching instruction of the group g is issued on the switch screen, the switching
process is activated, and the flag Msel (g) of the group g to be switched is inverted in step S30,
and the node which has been the standby system in the group g It becomes a flag state. Next, the
CPU 10 sends a switching instruction to switch to the active system to the node instructed as the
10-04-2019
18
active system with the flag Msel (g). The card I / O of the switching node (node that becomes the
active system) that has received the switching instruction sends a switching request to the other
node (step S40). The flag Msel (g) is "0" when the node with the lower node number is set as the
active node, and the flag Msel (g) is "1" when the node with the lower node number is set as the
standby node. However, the reverse is also possible.
[0042]
The card I / O of the node on the switched side (the node that was the active system), which is
the opposite node, receives the switching request (step S50), performs time adjustment until
reaching the switchable time in step S51, and switching When the available time has been
reached, a response transmission is sent out to the node which has sent the switching request in
step S52. Next, in step S52, the transmission of the frame sent to the A bus 26 from the node
switched is stopped. The response transmission is received by the card I / O of the switching
node (step S41), and it is determined in step S42 whether or not there is a response to the
switching request. Here, if it is determined that there is a response, the process proceeds to step
S43, where the frame transmission to the A bus 26 is started. The frame in this case is the frame
assigned to the node to be switched. The frame transmission stop process in step S52 and the
frame transmission start process in step S43 are performed in the same DAC cycle. When the
frame transmission start process is completed in step S43, a result indicating that the node
switched in step S44 has been switched to the operation system node is reported. The CPU 10
having received this report confirms that the node of the group g is switched in step S32,
updates and displays the display of the group g on the switch screen shown in FIG. 10 in step
S33, and performs switching processing Ends.
[0043]
An example of the timing adjustment process executed in step S51 in the switching process is
shown in FIG. In the example shown in FIG. 12, a case is shown in which the operation system is
switched from "DSP (3)" which is "node 3" to "DSP (4)" which is "node 4" in "group 1". In FIG. 12,
the timing at which each node outputs a frame is the same as the timing shown in FIG. Here,
when the cursor is placed on "DSP (4)" on the switch screen shown in FIG. 10 and the enter key is
pressed, the switching process shown in FIG. It is assumed that the switching request is 3 ". In
this case, since the time ta is within the prohibition time to prohibit switching as shown in the
drawing, in the first example shown as Example 1, the timing is adjusted until the prohibition
time ends and response transmission and frame transmission stop at time tb Processing is
performed. Then, the “node 4”, which is the switching node that has received the response
10-04-2019
19
transmission, immediately executes processing of frame transmission start. As a result, in the
same DAC period starting from time t0, the frame transmission stop process in “node 3” and
the frame transmission start process by “node 4” are executed. As a result, in the next DAC
cycle started from time t10, the "node 4" transmits the frame # 2 to the A bus 26 without
interruption.
[0044]
Further, in the second example shown as Example 2 in FIG. 12, when “node 3” which is a node
to be switched at timing of ta receives the switching request, time ta prohibits switching as
shown in the figure. Since it is within the prohibition time, the timing of the timing adjustment is
performed until the predetermined time provided at the end of the DAC period is reached, and
processing of response transmission and frame transmission stop is executed at time tc. Then,
the “node 4”, which is the switching node that has received the response transmission,
immediately executes processing of frame transmission start. As a result, in the same DAC period
starting from time t0, the frame transmission stop process in “node 3” and the frame
transmission start process by “node 4” are executed. As a result, in the next DAC cycle started
from time t10, the "node 4" transmits the frame # 2 to the A bus 26 without interruption. The
predetermined time provided at the end of the DAC period is set as a margin time provided for
stable operation of transmission of acoustic signals of 512 channels in the A bus 26.
[0045]
Next, FIG. 13 shows a flowchart of the card separation instruction process of the (i) -th node
performed when hot-removing a card that constitutes a grouped node. The card disconnection
instruction process of the (i) -th node is activated when a card disconnection instruction is issued,
and in step S60, detection processing of the group g to which the node instructed to be
disconnected belongs is performed. In this detection processing, it is determined whether the
group g is detected and whether the group g is enabled (Men (g) = 1). It is assumed that the card
is attached to two nodes forming the group g. Here, if it is determined that the group g is enabled
and the flag Men (g) is "1", the process proceeds to step S62, and it is determined whether the (i)
th node instructed to release the card is active. Here, if it is determined that the (i) th node is set
to be active, the process proceeds to step S63, and the switching process shown in FIG. 11 of the
node set as the active system is performed.
[0046]
10-04-2019
20
As a result, it is determined in step S64 whether the node to be separated is switched to the
standby system and switched. Here, if it is determined that the switching to the standby system is
completed, the process proceeds to step S65 where the data signal line of the card in the node
instructed to be disconnected is disconnected. Next, the power supply to the card whose data
signal line has been disconnected in step S66 is stopped. Furthermore, in order to release the
enable state, the flag Men (g) is inverted to "0" in step S67. Then, in step S68, the card whose
power supply has been stopped is updated as "switchable", and the card separation instruction
process of the (i) th node is completed. If it is determined in step S61 that there is no group g or
that group g is not enabled, the process branches to step S69, and the power of the acoustic
signal processing apparatus 1 is turned off to instruct removal of the card. The error processing
is performed and the card separation instruction process of the (i) th node ends. If it is
determined in step S62 that the (i) th node is not active, the processing in steps S63 and S64 is
skipped because it is not necessary to perform the switching process. Furthermore, when it is
determined in step S64 that the switching process is not completed, the process branches to step
S69, the above-mentioned error process is performed, and the card separation instruction
process of the (i) th node is completed. In the above processing, disconnection of the data signal
line in the card and stopping of the power supply are performed by the hot swap circuit 25c of
the card I / O (i).
[0047]
Next, FIG. 14 shows a flowchart of the (i) th slot card installation process performed when the
card is installed in the (i) th node slot. When the card is inserted into the slot of the (i) th node,
the (i) th slot card installation process is started, and the card is inserted from the hot swap
circuit 25c of the card I / O (i) in step S70. Power is supplied to enable the card. Next, in step
S71, the data signal line is connected by the hot swap circuit 25c. Then, in step S72, detection
processing of the group g to which the (i) th node to which the card is attached belongs is
performed. If it is determined in step S73 that the group g is detected in this detection
processing, the process proceeds to step S74, and it is determined whether or not it matches the
card type of the detected group g. Here, if it is determined that the type of installed card matches
the card type of the detected group g, the process proceeds to step S75, and a program
corresponding to the processing type of the node of the group g and the nodes of the group g
The current signal processing parameters stored in the prepared current memory (for the card)
are loaded to the mounted card.
[0048]
10-04-2019
21
Next, since the card is attached to two nodes constituting the group g, the flag Men (g) is inverted
to "1" at step S76. Further, since the group g is duplicated in step S77, the display update for
displaying the switch screen of the group g on the switch screen shown in FIG. 10 and the card
type in the (i) node are displayed on the display screen of the system settings. The display update
is performed, and the (i) slot card installation process ends. If it is determined in step S73 that
there is no group to which the mounted card belongs, and if it is determined that the type of the
mounted card does not match the detected card type of group g in step S74. In step S77, only the
display update for displaying the card type in the (i) th node is performed on the display screen
of the system setting, and the (i) th slot card installation processing ends.
[0049]
In the acoustic signal processing apparatus 1 of the present invention, in the node in which the
operation system and the standby system are duplexed, when a failure occurs in the operation
system node and the allocated frame can not be transmitted, the standby system node An
acoustic signal can be transmitted in a frame assigned instead of the active node. FIG. 15 shows a
flowchart of the DAC process of the group g standby node that performs such a process. The
group g standby node each DAC process is activated when the standby node reaches the timing
to send a frame, and in step S80, it is detected whether the operation node has sent a frame. In
this detection process, detection of a frame is performed within a predetermined detection time,
and it is determined in step S81 whether a frame is detected in the detection process.
[0050]
Here, if it is determined that a frame has been detected, the process proceeds to step S 82, part
of data in the detected frame is fetched, and data of the processing result in the standby node is
compared with the data content in step S 83. . Next, whether or not the data contents match is
determined in step S84, but since the processing contents at the active node and the standby
node are the same, the data contents match at normal times. Here, if it is determined that the
data contents match, the active node is operating normally, and the DAC processing of the
standby node of group g is terminated as it is. If it is determined in step S84 that the data
contents do not match, a warning of "processing result mismatch" is displayed on the display unit
14 because there is a possibility that there is an abnormality in the active node, and the group is
displayed. g standby node Ends each DAC process. By this, the user is made to confirm the
operation of each node of the group g.
10-04-2019
22
[0051]
Furthermore, if it is determined in step S81 that a frame is not detected, it is determined that a
failure has occurred in the active system of group g, and the process branches to step S86 to
cancel the enabled state of group g. At the same time, the flag Men (g) is inverted to “0”, and
the flag Msel (g) is inverted in order to change the standby node to the active node instead of the
failed node. Next, in step S87, the frame which has been assigned to the group g is sent from the
node which has been the standby system up to now instead of the failed node. Then, in step S88,
the card of the node which has been the active system is separated, and the node number and
abnormality of the node which has been the active system are displayed on the display 14, and
the group g standby node each DAC processing Finish. As a result, the user can replace a card
having an abnormality.
[0052]
Here, a specific example of the frame detection process executed in step S80 and step S81 will be
described with reference to the timing chart of the frame signal shown in FIG. In FIG. 16, “group
1” is shown as an example, focusing on the frame # 2 assigned to “group 1”. In normal
operation, when transmission of frame # 1 ends, the frame signal of frame # 1 rises at time ts,
and this is detected in “node 3” and “node 4” which are duplexed in “group 1” The "node
3" of the system causes the frame signal of frame # 2 to fall to transmit frame # 2 and starts
transmission of frame # 2. Then, when the transmission of frame # 2 ends, the frame signal of
frame # 2 is raised. Then, the rising edge of the frame signal of frame # 2 is detected at "node 5"
which transmits the next frame # 3, and "node 5" lowers the frame signal of frame # 3 to
transmit frame # 3. Start sending frame # 3.
[0053]
By the way, at the time of failure when transmission of frame # 1 ends, the frame signal of frame
# 1 rises at time ts when failure occurs in the active node "node 3" of "group 1", but "node 3" The
frame signal of frame # 2 is not dropped so that frame # 2 is transmitted, and transmission of
frame # 2 is not performed. Thus, at the time of failure, transmission of frame # 2 is lost, and
frames subsequent to frame # 2 can not be transmitted. Therefore, it is detected whether or not
the frame signal of frame # 2 falls in a period of detection period ΔT in which “node 4” in the
10-04-2019
23
standby system of “group 1” sees a margin, and frame # 2 is detected within the period of
detection period ΔT. When confirming that the frame signal does not fall, the "node 4" of the
standby system causes the frame signal of frame # 2 to fall so as to transmit frame # 2 and starts
transmission of frame # 2. As a result, since frame # 2 is sent out, frame # 2 and subsequent
frames are also sent out normally. Note that the acoustic signal transmitted in frame # 2 is an
acoustic signal on which the same signal processing as the signal processing of “node 3” is
applied to the same input at “node 4”, and a failure occurs in “node 3”. The acoustic signal
will be sent out without interruption. Further, the detection period ΔT is set to be longer than at
least the margin time between frames.
[0054]
The acoustic signal processing device 1 according to the present invention described above can
duplex a node provided with a card into an operation system and a standby system. The same
nodes and the same signal processing parameters are supplied to the dual nodes of the active
system and the standby system, and when the program is loaded, the same program is loaded
and the same signal processing is performed. Only the nodes of the system are allowed to output.
In addition, the user can arbitrarily switch between the active system and the standby system in
the dual nodes of the active system and the standby system. In this case, switching between the
operation system node and the standby system node is performed in the same sampling (DAC)
cycle to prevent the acoustic signal from being interrupted. Furthermore, the cards in the dual
operation system and the standby system can be hot-plugged, and the card can be removed from
the slot by instructing the user to remove the card to be removed. In this case, when the card to
be removed is the active system, the standby system is automatically switched to the active
system by the process executed when the separation instruction is issued. Furthermore, when a
failure occurs in a dual operation system node, instead of the operation system node, the standby
system node sends out the frame of the acoustic signal processed by the signal processing to the
A bus 26 without interrupting the acoustic signal. can do. Although the number of nodes in the
acoustic signal processing apparatus 1 is eight, the number of nodes is not limited to this and
may be sixteen or twenty-four. Further, although the maximum number of channels transmitted
by the A bus 26 is 512 channels, the number of channels is not limited to this and may be 1024
channels or 2048 channels.
[0055]
It is a block diagram which shows the structure of the acoustic signal processing apparatus
which is an Example of this invention. It is a block diagram which shows the detail of a structure
10-04-2019
24
of the node in the acoustic signal processing apparatus which is an Example of this invention. It
is a figure which shows the algorithm of the mixing process in case the acoustic signal
processing apparatus which is an Example of this invention is made into the mixing processing
apparatus. It is a figure which shows the data structure of the current memory in the sound
signal processing apparatus which is an Example of this invention. FIG. 7 is a diagram showing
timings at which each node outputs a frame in the acoustic signal processing device according to
the embodiment of the present invention. It is a figure which shows an example of the inputoutput channel number of "node 0" thru | or "node 7" in the acoustic signal processing apparatus
which is an Example of this invention. It is a flowchart of the system setting process which CPU
performs in the sound signal processing apparatus which is an Example of this invention. It is a
figure which shows the display screen of the system setting displayed in the sound signal
processing apparatus which is an Example of this invention. It is a flowchart of the parameter
value change process which CPU performs in the sound signal processing apparatus which is an
Example of this invention. It is a figure which shows the switch screen displayed in the sound
signal processing apparatus which is an Example of this invention. It is a flowchart of the switch
process (with switch operation of the group g) performed in the acoustic signal processing
apparatus which is an Example of this invention. It is a figure which shows the switching timing
of DSP (1), (2) (frame # 2) in the acoustic signal processing apparatus which is an Example of this
invention. It is a flowchart of the card separation instruction | indication process of the (i) th
node performed in the acoustic signal processing apparatus which is an Example of this
invention. It is a flowchart of the (i) slot card mounting process performed in the acoustic signal
processing apparatus which is an Example of this invention. It is a flowchart of group g standby
node each DAC process performed in the acoustic signal processing apparatus which is an
Example of this invention. It is a timing chart which shows the example of the frame detection
processing in the sound signal processing device which is an example of the present invention.
FIG. 12 is a block diagram showing a configuration of an example of a musical tone synthesizing
apparatus in which conventional acoustic signals are transmitted and received via a bus. FIG. 18
is a timing chart of frame transmission in the conventional tone synthesizing system shown in
FIG.
Explanation of sign
[0056]
Reference Signs List 1 sound signal processing device, 10 CPU, 11 flash memory, 12 RAM, 13
external storage device, 14 display unit, 15 panel switch unit, 16 other I / O unit, 17 MIDI I / O
unit, 18 sound system, 19 CPU Bus, 20 sound signal processing units, 21 analog input / output
nodes, 22a analog input cards, 22b analog input cards, 23a DSP cards, 23b DSP cards, 23c DSP
cards, 24 digital input / output cards, 25 card I / O, 25a control I / O, 25b Audio I / O, 25c Hot
Swap Circuit, 26 A Bus, 27 Cards, 27a Control Microcomputer, 27b Audio Circuit, 28 Word Clock
10-04-2019
25
Generator, 30 Analog Inputs, 31a Analog Inputs, 31b Analog Inputs , 32 digital inputs, 33 input
patch, 34a input channel section, 34b input channel section, 35 input channel section, 36 MIX
bus, 37a output channel section, 37b output channel section, 38 output patch, 39 analog output
section, 40 digital output section, 202 MIDI I / O, 204 other I / O, 206 panel switch unit, 208
display, 210 external storage device, 212 CPU, 214 flash memory, 216 RAM, 218 CPU bus, 220
sound system, 250 sound source unit, 251 word clock generator , 252, 254 sound source LSI,
256, 258, 260 expansion board, 262 A bus, 264 DAC, 268 word clock external input terminals
10-04-2019
26
Документ
Категория
Без категории
Просмотров
0
Размер файла
46 Кб
Теги
description, jp2008252169
1/--страниц
Пожаловаться на содержимое документа