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DESCRIPTION JP2011091530

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DESCRIPTION JP2011091530
An LC circuit can be configured to shift an audio signal pulse by a predetermined phase
according to a change in capacitance without using a unitized dedicated delay line. A fixed pole
120 having capacitance with a diaphragm is divided into a plurality of fixed pole pieces 121 to
124, and each fixed pole piece 121 to 124 is serially connected via a coil (inductor element) 151.
It connects and the LC circuit 12 is comprised. [Selected figure] Figure 2
コンデンサマイクロホン
[0001]
The present invention relates to a condenser microphone, and more particularly to a condenser
microphone in which an electrostatic capacitance change of a microphone unit is digitized to
obtain an audio signal.
[0002]
The condenser microphone is provided with a kind of condenser consisting of a combination of a
diaphragm and a fixed electrode, and in order to extract as an electrical signal a change in
capacitance due to displacement of the diaphragm due to sound waves, a direct current is
provided between the diaphragm and the fixed electrode. It is necessary to apply a voltage.
This DC voltage is called polarization voltage, and there are a method of applying a voltage from
the outside of the microphone unit and a method of applying a polarization voltage by an electret
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material.
[0003]
In the condenser microphone, since the impedance between the diaphragm and the fixed
electrode is very high, a voltage signal of a predetermined level is obtained using an impedance
converter such as a FET or a vacuum tube.
[0004]
However, the above-mentioned conventional condenser microphone is susceptible to an external
electric field or magnetic field when converting a change in electrostatic capacitance into a
voltage.
In addition, since the impedance converter is used, for example, when the ambient humidity is
high, the impedance converter may cause charge leakage and generate noise.
[0005]
Furthermore, although the electret condenser microphone can be miniaturized, for example, for
portable telephones, the electret material is susceptible to heat, and therefore, when it is
mounted on a substrate, the reflow soldering method can not be applied. Therefore, there is a
problem that it must be mounted separately from chip components such as resistors and
capacitors.
[0006]
Therefore, in order to solve the above-mentioned problems, the present applicant has proposed,
as Patent Document 1, a condenser microphone in which a capacitance change is converted to a
digital signal to obtain an audio signal.
[0007]
That is, according to the invention described in Patent Document 1, a first clock output means for
outputting a first clock pulse, a second clock output means for outputting a second clock pulse
having a frequency lower than that of the first clock pulse, and a capacitor An audio signal
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output circuit comprising an LC circuit including a capacitance of a microphone unit and an
inductance of a coil, and shifting the second clock pulse by a predetermined phase according to a
change in the capacitance and outputting it as an audio signal; A reference signal output circuit
that outputs two clock pulses as a reference signal for the audio signal, and the audio signal and
the reference signal, and when the audio signal has a phase lead with respect to the reference
signal, a phase advancing pulse A phase comparison means for outputting a signal and
outputting a delayed pulse signal when there is a phase delay; A first AND circuit outputting an
addition pulse by ANDing with one clock pulse; a second AND circuit outputting a subtraction
pulse by ANDing the delayed pulse signal and the first clock pulse; It is characterized in that it
has an addition / subtraction counter which counts pulses and subtraction pulses and outputs an
audio data signal.
[0008]
According to this, since the change in capacitance is not converted into a voltage, it is not easily
influenced by the surrounding electromagnetic field.
In addition, noise due to charge leakage of the impedance converter does not occur.
Furthermore, since the polarization voltage by an electret material etc. is not required, the
advantage said that the mounting method by a reflow soldering method will also be attained with
chip components, such as resistance and a capacitor | condenser, is acquired.
[0009]
JP 2003-23691 A
[0010]
By the way, as a delay line for delaying a pulse, a dedicated unitized delay line is commercially
available (see, for example, an output delay line of "TDP" series manufactured by Elmeck Corp.).
[0011]
In practicing the invention described in Patent Document 1, if the microphone unit is connected
in series to the capacitor using the dedicated delay line, the voice signal pulse is shifted by a
predetermined phase according to the change in capacitance. The circuit is easily obtained.
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[0012]
However, since the dedicated delay line on the market is unitized, using it is subject to
restrictions such as component arrangement in designing the microphone unit, and in some
cases, the LC circuit may be incorporated in the microphone unit. The problem arises that it can
not be incorporated.
[0013]
Therefore, an object of the present invention is to provide an LC circuit which shifts an audio
signal pulse by a predetermined phase according to a change in capacitance without using a
unitized dedicated delay line in the invention described in Patent Document 1 above. It is to be
able to configure.
[0014]
In order to solve the above problems, according to the present invention, there is provided a
microphone unit formed by arranging a diaphragm and a fixed pole both facing each other at a
predetermined interval, and a first clock pulse being output. A clock output unit, a second clock
output unit for outputting a second clock pulse having a frequency lower than that of the first
clock pulse, and an LC circuit including an electrostatic capacity of the microphone unit and an
inductance of a coil; An audio signal output circuit which shifts a clock pulse by a predetermined
phase according to the change of the capacitance and outputs it as an audio signal; a reference
signal output circuit which outputs the second clock pulse as a reference signal for the audio
signal; Obtaining a signal and the reference signal, and when the audio signal has a phase lead
with respect to the reference signal, A phase comparison means for outputting a delayed pulse
signal when there is a phase delay, a first AND circuit for outputting an added pulse by the
logical product of the advance pulse signal and the first clock pulse, and A second AND circuit for
outputting a subtraction pulse by ANDing the delayed pulse signal and the first clock pulse; and
an addition / subtraction counter for counting the addition pulse and the subtraction pulse and
outputting an audio data signal; In the capacitor microphone, the fixed pole is divided into a
plurality of fixed pole pieces, and the fixed pole pieces are connected in series via the coil to
constitute the LC circuit.
[0015]
According to a preferred aspect of the present invention, the fixed pole is divided into at least
three or more at equal angles so that the fixed pole pieces have the same area.
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[0016]
Moreover, it is preferable that the electrode terminal is pulled out toward the radial direction
outer side from the periphery of each said fixed pole piece, and the said coil is connected
between said electrode terminals.
[0017]
According to the present invention, by dividing the fixed pole into a plurality of fixed pole pieces
and connecting each fixed pole piece in series via the coil (inductor element), an audio signal
pulse can be obtained without using a dedicated delay line. Can be easily obtained by shifting the
phase by a predetermined phase according to the change in capacitance.
Moreover, since it is only necessary to incorporate a small coil into the fixed pole, the degree of
freedom in the design of the microphone unit can be increased.
[0018]
In addition, if the electrode terminal is drawn radially outward from the peripheral edge of each
fixed pole piece, the coil can be easily attached between the fixed pole pieces, and the workability
can be improved.
[0019]
FIG. 1 is a block diagram of a condenser microphone according to an embodiment of the present
invention.
The top view which shows the fixed pole in the said capacitor | condenser microphone.
The equivalent circuit schematic of LC circuit which consists of the fixed pole piece and coil
which were divided | segmented from the said fixed pole.
The wave form diagram which shows the phase relationship of a reference signal and an audio |
voice signal.
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The wave form diagram which shows an advance phase pulse and a phase delay pulse.
The wave form diagram which shows a clock pulse, an addition pulse, and a subtraction pulse.
[0020]
Next, embodiments of the present invention will be described with reference to FIGS. 1 to 6, but
the present invention is not limited thereto.
[0021]
First, referring to the drawing, a condenser microphone 1 according to this embodiment includes
an audio signal output circuit 10, a reference signal output circuit 20, a clock pulse generator 30
for generating high-speed clock pulses, and predetermined clock pulses. , A phase comparator 40
for comparing the phase of the audio signal and the reference signal, and PNM for converting the
pulse output from the phase comparator 40 into an addition pulse and a subtraction pulse. The
conversion unit 50 and an addition / subtraction counter 60 which counts the added pulse and
the subtracted pulse and outputs the audio data.
[0022]
The audio signal output circuit 10 includes a condenser microphone unit (hereinafter, referred to
as “microphone unit”) 11 and an LC circuit 12 including electrostatic capacitance (C) of the
microphone unit 11 and inductance (L) of a coil.
[0023]
As schematically shown in FIG. 3, by disposing the diaphragm 130 and the fixed pole 120
stretched on the diaphragm ring 131, the microphone unit 11 is opposed to each other via an
electrically insulating spacer ring (not shown). Although the configuration is simple, the
configuration may be simple, and no polarization voltage by an electret material or the like is
required.
[0024]
As shown in FIG. 2, the fixed pole 120 is divided into a plurality of fixed pole pieces in order to
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configure the LC circuit 12.
Although the number of divisions and the area of each fixed pole piece may be arbitrarily
determined, it is preferable that the area of each fixed pole piece is approximately the same as
three or more.
[0025]
In this embodiment, the fixed pole 120 is made of copper foil formed on the printed circuit board
140, and is divided into four fixed pole pieces 121, 122, 123, 124 having equal areas at equal
angles of 90 °.
As a result, as shown in FIG. 3, four electrostatic capacitances C1 exist in parallel between the
fixed electrode 120 and the diaphragm 130.
[0026]
Of the four fixed pole pieces, two adjacent fixed pole pieces are selected as the signal input side
(IN) and the signal output side (OUT).
In this embodiment, the fixed pole piece 121 is a signal input side (IN), the fixed pole piece 124
is a signal output side (OUT), and the fixed pole pieces 121, 122, 123, 124 are connected via a
coil (inductor element) 151. And connected in series.
[0027]
That is, the coils 151 are connected between the fixed pole piece 121 and the fixed pole piece
122, between the fixed pole piece 122 and the fixed pole piece 123, and between the fixed pole
piece 123 and the fixed pole piece 124, respectively.
The inductance L1 of each coil 151 is preferably substantially the same.
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[0028]
Thus, the fixed pole 120 opposed to the diaphragm 130 is divided into, for example, four fixed
pole pieces 121 to 124, and each is connected in series via the coil 151, without using a
dedicated delay line. As illustrated in FIG. 3, an LC circuit (delay line) 12 is formed by the
inductance L1 of the coil 151 and the electrostatic capacitance C1 existing between the
diaphragm 130 and the fixed pole pieces 121 to 124.
[0029]
Note that, as shown in FIG. 2, tongue pieces 141 to 144 extending outward in the radial direction
are continuously provided on the printed circuit board 140 for each fixed pole piece 121 to 124,
and each fixed pole piece is attached to each tongue piece 141 to 144. By forming the electrode
terminals 121a to 124a drawn out from the periphery of the electrodes 121 to 124, the coil 151
can be easily connected between the fixed pole pieces.
[0030]
In this embodiment, the reference signal output circuit 20 also includes an LC circuit 23 for
reference signal phase adjustment, which includes the capacitance C2 of the variable capacitor
21 and the inductance L2 of the coil 22.
[0031]
For example, a crystal oscillator is used for the clock pulse generator (first clock output means)
30, and a high speed (high frequency) clock pulse CK1 is used as the frequency divider (second
clock output means) 31 and the PNM conversion unit 50. give.
The frequency divider 31 divides the clock pulse CK1 at a predetermined division ratio and
converts it to a low speed (low frequency) clock pulse CK2.
[0032]
The clock pulse CK2 is input to the LC circuit 12 of the audio signal output circuit 10 and the LC
circuit 23 of the reference signal output circuit 20 via the voltage amplifier A and the protective
resistor R, respectively.
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[0033]
In the audio signal output circuit 10, the electrostatic capacitance C1 of the microphone unit 11
changes according to the input sound pressure, so that the clock pulse CK2 is shifted in phase
according to the electrostatic capacitance C1. The signal is then applied to one input terminal 40
a of the phase comparator 40.
[0034]
In the reference signal output circuit 20, the clock pulse CK2 is shifted in phase by the time
constant set in the LC circuit 23, but its phase is constant except at the time of phase adjustment
by the variable capacitance capacitor 21, As a reference signal for the signal, it is also applied to
the other input terminal 40b of the phase comparator 40 via the voltage follower F.
[0035]
The phase comparator 40 compares the phase of the audio signal from the audio signal output
circuit 10 with the phase of the reference signal from the reference signal output circuit 20, and
when the audio signal has a phase lead with respect to the reference signal, the first output
terminal 40c. The phase advance pulse S1 is output to the second output terminal 40d when the
voice signal has a phase delay with respect to the reference signal.
[0036]
In this embodiment, the phase comparator 40 is a phase frequency comparator that operates at
the rising edge of the input waveform, and may use, for example, an integrated circuit MC4044
manufactured by Motorola, Inc.
[0037]
A PNM (Pulse Number Modulation) conversion unit 50 includes first to third three AND circuits
51 to 53 of two-input type and one exclusive OR circuit 54, and the phase advance pulse S1 and
the phase advance pulse S1 and The pulse width of the slow pulse S2 is converted to the number
of pulses of the clock pulse CK1, and the addition pulse P1 and the subtraction pulse P2 are
output.
[0038]
In order to perform this pulse number conversion with high accuracy, it is necessary to make the
pulse width of the clock pulse CK1 sufficiently shorter than the pulse widths of the advancing
pulse S1 and the lagging pulse S2.
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[0039]
One input terminal of the first AND circuit 51 is connected to the first output terminal 40 c of the
phase comparator 40, and the other input terminal is connected to the output terminal of the
third AND circuit 53.
One input terminal of the second AND circuit 52 is connected to the second output terminal 40 d
of the phase comparator 40, and the other input terminal is connected to the output terminal of
the third AND circuit 53.
[0040]
One input terminal of the third AND circuit 53 is connected to the clock pulse generator 30, and
the other input terminal is connected to the output terminal of the exclusive OR circuit 54.
One input terminal of the exclusive OR circuit 54 is connected to the first output terminal 40 c of
the phase comparator 40, and the other input terminal is connected to the second output
terminal 40 d of the phase comparator 40.
[0041]
The truth value of the exclusive OR circuit 54 has an output of [0] when the input is [0,0] or [1,1]
and an output of [0,1] or [0,1] when the input is [1,0]. 1].
[0] is synonymous with L level, and [1] is synonymous with H level.
[0042]
In this embodiment, the addition / subtraction counter 60 is an up / down binary counter, and
performs reversible addition / subtraction based on the addition pulse signal P1 from the PNM
conversion unit 50 and the subtraction pulse signal P2, and Output as 12-bit or 16-bit parallel
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data.
[0043]
The addition / subtraction counter 60 holds the state before the phase of the audio signal
changes, and counts up or down only when the phase change occurs.
Further, in this embodiment, the first output terminal OUT1 outputs the digital audio data as it is,
and the second output terminal OUT2 converts the audio data to an analog signal by the D / A
converter 61 and outputs the analog signal. There is.
[0044]
Next, the operation of the condenser microphone 1 will be described with reference to FIGS. 4 to
6.
The same clock pulse CK2 obtained by dividing the clock pulse CK1 in a predetermined manner
is supplied from the frequency divider 31 to the audio signal output circuit 10 and the reference
signal output circuit 20.
[0045]
In the audio signal output circuit 10, the clock pulse CK2 is given to one input terminal 40a of
the phase comparator 40 as an audio signal whose phase is shifted by the LC circuit 12 in
proportion to the input sound pressure of the microphone unit 11. .
[0046]
On the other hand, in the reference signal output circuit 20, the clock pulse CK2 is given to one
input terminal 40a of the phase comparator 40 as a reference signal whose phase is shifted by a
fixed amount in the LC circuit 23.
[0047]
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FIG. 4 shows the phase relationship between the reference signal and the audio signal.
FIG. 4 (a) is a reference signal CK3, and FIGS. 4 (b) and 4 (c) are audio signals CK4.
While the phase of the reference signal CK3 is fixed, the phase of the audio signal CK4 is
changed by the input sound pressure of the microphone unit 11.
[0048]
FIG. 4 (b) shows a state in which the audio signal CK4 has a lead phase of + dθ with respect to
the reference signal CK3, and FIG. 4 (c) shows a delay phase of -dθ with respect to the reference
signal CK3. It shows the state you have.
[0049]
The phase comparator 40 outputs the advance pulse S1 to the first output terminal 40c when the
voice signal CK4 is in the lead phase with respect to the reference signal CK3, and when the voice
signal CK4 is in the delay phase with respect to the reference signal CK3, The slow pulse S2 is
output to the second output terminal 40d.
[0050]
FIG. 5 (a) shows the phase advancing pulse S1, and FIG. 5 (b) shows the phase delaying pulse S2.
In this example, the lead phase is in sections T1 and T3 and the delay phase is in section T2, and
the pulse width is proportional to the amount of phase shift.
That is, the audio signal CK4 is PWM (Pulse Width Modulation) modulated by the phase
comparator 40.
[0051]
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The leading pulse S1 is applied to one input terminal of the first AND circuit 51, and the delayed
pulse S2 is applied to one input terminal of the second AND circuit 52.
Since the phase advance pulse S1 and the phase delay pulse S2 are alternately output when the
phase comparator 40 is operating normally, the output of the exclusive OR circuit 54 holds [1].
[0052]
Therefore, the clock pulse CK1 shown in FIG. 6A is supplied from the third AND circuit 53 to the
other input terminals of the first AND circuit 51 and the second AND circuit 52.
[0053]
Thus, the first AND circuit 51 obtains the logical product of the clock pulse CK1 and the advance
pulse S1, and applies the addition pulse P1 shown in FIG. 6B to the UP terminal of the addition /
subtraction counter 60.
Further, the second AND circuit 52 obtains the logical product of the clock pulse CK1 and the
delayed pulse S2, and applies the subtraction pulse P2 shown in FIG. 6C to the DOWN terminal of
the adding and subtracting counter 60.
[0054]
Thus, PNM (Pulse Number Modulation) modulation is performed by the first and second AND
circuits 51 and 52, and the pulse widths of the phase advance pulse S1 and the phase delay pulse
S2 are converted into the number of pulses of the clock pulse CK1. .
[0055]
An addition / subtraction counter (up / down binary counter) 60 performs reversible addition /
subtraction based on the addition pulse signal P1 and the subtraction pulse signal P2, and in this
embodiment, the voice data is parallel data of 12 bits or 16 bits. Output as
[0056]
According to this embodiment, digital audio data is output as it is from the first output terminal
OUT1, and audio data is converted to an analog signal and output from the second output
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terminal OUT2. Either side can be selected on the part side.
[0057]
Although the crystal oscillation circuit is used as the clock generator 30 in the above
embodiment, a CR oscillation circuit, an LC oscillation circuit, a multivibrator or the like may be
used instead.
Further, the addition and subtraction counter 60 may be a microprocessor or the like.
Furthermore, although the phase comparator 40 may be an analog type phase comparator, in
this case, for example, an output signal is A / D converted and input to the AND circuit.
[0058]
The voltage amplifier A, the protection resistor R, the voltage follower F, the LC circuit 23 of the
reference signal output circuit 20, the third AND circuit 53, the exclusive OR circuit 54 and the D
/ A converter 61 are optional in the present invention. Component.
[0059]
10 voice signal output circuit 11 microphone unit 12 LC circuit 120 fixed pole 121 to 124 fixed
pole piece 130 diaphragm 151 coil (inductor element) 20 reference signal output circuit 23 LC
circuit 30 clock pulse generator (first clock output means) 31 Divider (2nd clock output means)
40 phase comparator 50 PNM conversion unit 51-53 AND circuit 54 exclusive OR circuit 60
addition / subtraction counter S1 phase advance pulse S2 lagging pulse P1 addition pulse P2
subtraction pulse
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