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DESCRIPTION JP2018075450

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DESCRIPTION JP2018075450
Abstract: The present invention provides an ultrasound diagnostic device that overcomes the
severe limitations and drawbacks associated with adopting a conventional architecture and signal
processing paradigm. Kind Code: A1 On-chip signal processing can be employed during the
receive signal path, for example to reduce data bandwidth, to implement a single-chip ultrasound
imaging solution, and use high-speed serial data modules The data can then be moved to all offchip receive channels as digital data streams. Digitization of the on-chip receive signal allows
advanced digital signal processing to be performed on-chip, allowing complete integration of the
entire ultrasound imaging system on a single semiconductor substrate. Novel waveform
generation techniques, transducer configurations and biasing methodologies are likewise
disclosed. The HIFU method can be additionally or alternatively employed as a component of the
ultrasound on-chip solution. [Selected figure] Figure 2A.
Ultrasonic device
[0001]
Cross-Reference to Related Applications [0001] This application is filed on March 15, 2013
under Attorney Docket No. B1348.70006US00, which is incorporated herein by reference in its
entirety, “MONOLITHIC ULTRATIVE IMAGING DEVICES, Claim the benefit under the US Patent
Act of US Provisional Patent Application No. 61 / 798,851, entitled SYSTEMS AND METHODS.
[0002]
Aspects of the present disclosure relate to devices, systems, and methods for imaging and / or
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treatment (eg, ultrasonic imaging and / or treatment techniques).
For example, certain aspects of the architecture and techniques disclosed herein allow the entire
ultrasonic imaging system to be integrated on a single semiconductor substrate. Thus, many of
the features and methodologies described herein relate to single-chip ultrasonic imaging
solutions, or to devices and systems in which at least a substantial portion of an ultrasonic
imaging system is provided on a single chip.
[0003]
Conventional ultrasound scanners have a hardware configuration that can be used for image
processing, such as line scanning with beamforming for transmit and receive operations, which
limits the type of imaging algorithm.
[0004]
In addition, the cost and scalability of ultrasonic scanners are approaching the limits of currently
prevailing piezoelectric transducer technology.
Piezoelectric transducers are still made using the "dice and fill" manufacturing process, where
individual piezoelectric elements are cut and then individually placed on a substrate to Form.
Such processes tend to be expensive, uneven, and not scalable for machining and wiring.
[0005]
The problem of transporting multiple channels of analog signals from a piezoelectric transducer
array to an electronic circuit in an ultrasound scanner is larger, necessary to advance the
resolution of ultrasound imaging to enable high quality 3D volume imaging, The use of denser
transducer arrays has been very limited.
[0006]
Recent advances in the manufacturing technology of capacitive micromachined ultrasound
transducers (CMUTs) now enable the electronics industry to be promoted and allow high quality
ultrasound transducers to be fabricated within the same semiconductor factory.
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CMUT devices also have excellent bandwidth and acoustic impedance matching capabilities when
compared to piezoelectric transducers. Also, the increased flexibility available to design CMUT
arrays enables advanced array design techniques that can reduce imaging artifacts, improve
signal quality, and reduce the number of channels. However, ultrasonic imaging solutions using
CMUT arrays that have been proposed so far employ conventional architectures and signal
processing paradigms and thus have severe limitations and drawbacks.
[0007]
The present disclosure details various aspects of the novel paradigm for the design of
micromachined ultrasonic transducer based ultrasonic imaging devices. In some embodiments,
on-chip signal processing may be employed, for example, in the receive signal path to reduce
data bandwidth, and / or as a digital data stream using a high speed serial data module Data can
be moved to all off-chip receive channels. Digitization of the on-chip receive signal, according to
some embodiments of the present disclosure, allows advanced digital signal processing to be
performed on-chip, and thus, all ultrasonic imaging on a single semiconductor substrate
Complete or substantially complete integration of the system is possible. In some embodiments, a
complete "ultrasound system on chip" solution is provided.
[0008]
In some embodiments, the devices and architectures disclosed herein can be fully integrated in
one or more sophisticated manners, such as, for example, one or more synthetic aperture
techniques. Synthetic aperture techniques can allow, for example, the formation of high
resolution images from a collection of multiple receiving apertures.
[0009]
According to an aspect of the present technology, there is provided a method for processing a
signal from an ultrasonic transducer element, the method comprising ultrasonically using a
component integrated on the same semiconductor die as the ultrasonic transducer element.
Converting the analog signal corresponding to the output of the transducer element to a digital
signal. In some such embodiments, a digital representation of the output signal of the ultrasonic
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transducer is then generated on the semiconductor die, further processing of the signal on the
semiconductor die, and / or transmission of the digital signal from the semiconductor die
Becomes easier. In this manner, in some embodiments, the ultrasound device can be configured
to digitally communicate with other components on a single semiconductor die, integrated
transducers and circuits Including.
[0010]
In some embodiments, the method further includes transmitting data corresponding to the digital
signal from the semiconductor die as a high speed serial data stream using at least one additional
component integrated on the semiconductor die . In some embodiments, the method further
includes processing the digital signal to reduce its data bandwidth using at least one additional
component integrated on the semiconductor die. In at least some embodiments, such reduced
bandwidth facilitates transmission of semiconductor die digital data to other components.
[0011]
In some embodiments, the at least one additional component comprises a digital quadrature
demodulator. In some embodiments, the at least one additional component comprises an
averaging module. In some embodiments, the at least one additional component comprises a
matched filter (e.g., matched to a particular frequency), and in alternative embodiments
comprises a mismatched filter. In some embodiments, the at least one additional component
comprises a finite impulse response (FIR) filter. In some embodiments, the at least one additional
component comprises a half band decimation low pass filter. In some embodiments, the at least
one additional component may be a lamp circuit (eg, a digital lamp circuit), or a stretch circuit, to
convert a signal (eg, such as an LFM waveform) from time to frequency It has a dechirp module
that can be configured.
[0012]
In some embodiments, a method processes data corresponding to a digital signal to perform one
or more imaging functions using at least one additional component integrated on a
semiconductor die Further include. In some such embodiments, such performance of the imaging
function results in the formation of an ultrasound image or results in the formation of an
ultrasound image, and thus, in some embodiments, an integrated super. A sonic imaging device is
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formed on the semiconductor die. In some embodiments, one or more imaging functions include
apodization, back projection, fast hierarchy back projection, interpolation range movement or
other Fourier resampling techniques, dynamic focus, delay addition processing, and tomography
reprocessing. At least one imaging feature selected from a group of configurations. In at least
some embodiments, such features are used to provide advantageous image types, such as image
types that are medically relevant.
[0013]
In some embodiments, a method processes data corresponding to digital signals and implements
one or more back end processing functions using at least one additional component integrated
on a semiconductor die Further include. In some embodiments, one or more back-end processing
functions include down-range autofocus, cross-range autofocus, frequency dispersion
compensation, nonlinear apodization, remapping, compression, denoising, compounding,
Doppler, At least one back end processing function selected from the group consisting of
elastography, spectroscopy, and basis tracking.
[0014]
In some embodiments, the method further includes performing at least one digital signal
processing function using at least one microprocessor integrated on the semiconductor die. In
some embodiments, at least one microprocessor is used to reduce the bandwidth of data
corresponding to the digital signal. In some embodiments, at least one microprocessor is used to
perform one or more imaging functions. In some embodiments, the one or more imaging
functions are at least selected from the group consisting of apodization, backprojection, fast
hierarchical backprojection, Stolt interpolation, dynamic focus, delay addition processing, and
tomographic imaging Includes one imaging feature. In some embodiments, at least one
microprocessor is used to perform one or more back end processing functions. In some
embodiments, one or more back-end processing functions include down-range autofocus, crossrange autofocus, frequency dispersion compensation, nonlinear apodization, remapping,
compression, denoising, compounding, Doppler, At least one back end processing function
selected from the group consisting of elastography, spectroscopy, and basis tracking. In some
embodiments, including a microprocessor integrated on a semiconductor die further facilitates
the implementation of an ultrasound device on a single semiconductor die. For example, an
ultrasound imaging device configured to collect ultrasound data suitable for use in forming an
ultrasound image is implemented in some embodiments.
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[0015]
In some embodiments, the method processes the analog signal from the waveform prior to
converting the analog signal to a digital signal using at least one additional component integrated
on the semiconductor die It further includes separating. The separation of waveforms may be
used, in some embodiments, on signals representing multiple waveforms, and may include
separating selected signal components (e.g., selected frequencies). In some embodiments, at least
one additional component comprises an analog quadrature demodulator, and in some
embodiments comprises an analog dechirp module. In at least some embodiments, separation of
waveforms reduces the amount of data produced by the ultrasonic transducer element, thus
facilitating data processing and transfer of data to other components.
[0016]
In some embodiments, the ultrasonic transducer element comprises one or more micromachined
ultrasonic transducer cells. That is, the ultrasonic transducer cells individually or in combination
form an ultrasonic transducer element. Ultrasonic transducer elements can be formed from any
suitable combination of ultrasonic transducer cells when such cells are combined. In some
embodiments, one or more micromachined ultrasonic transducer cells comprise one or more
capacitive micromachined ultrasonic transducer (CMUT) cells. In some embodiments, one or
more micromachined ultrasonic transducer cells comprise one or more CMOS ultrasonic
transducer (CUT) cells. The use of such a cell in accordance with some embodiments facilitates
the integration of ultrasonic transducers with other components on a CMOS wafer.
[0017]
According to an aspect of the present technology, an ultrasonic device is provided, the ultrasonic
device being integrated on a semiconductor die with at least one ultrasonic transducer element
integrated on a semiconductor die, the ultrasonic transducer element being integrated And an
analog-to-digital (ADC) converter configured to convert an analog signal corresponding to the
output of the signal to a digital signal. In some embodiments, such an arrangement facilitates the
implementation of an integrated ultrasound device in which the ultrasonic transducer and
circuitry are integrated on a single semiconductor die. In some embodiments, such devices are
small in size due to the integration of components onto a single semiconductor die.
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[0018]
In some embodiments, the ultrasound device is further integrated on a semiconductor die and
configured to transmit data corresponding to digital signals from the semiconductor die as a high
speed serial data stream. Prepare. In some such embodiments, the use of a high speed data
module facilitates communication with off-chip components, thus extending the functionality of
the ultrasound device. For example, the ultrasound device in some embodiments is coupled to
and communicates with an external processing component, which in some embodiments is a
computer, a smartphone, or a tablet.
[0019]
In some embodiments, the ultrasound device further comprises at least one signal processing
module integrated on the semiconductor die and configured to process the digital signal to
reduce its data bandwidth. In such embodiments, the reduction in data bandwidth facilitates
communication with components external to the ultrasound device, which in some embodiments
are computers, smart phones, or tablets. , External processing components. In some
embodiments, communication includes transmitting data to an external component. In some
embodiments, at least one signal processing module comprises a digital quadrature demodulator.
In some embodiments, at least one signal processing module comprises an averaging module. In
some embodiments, the at least one signal processing module comprises a matched filter, and in
alternative embodiments comprises a mismatched filter. In some embodiments, at least one
signal processing module comprises a finite impulse response filter. In some embodiments, the at
least one signal processing module comprises a half band decimation low pass filter. In some
embodiments, at least one signal processing module comprises a dechirping module.
[0020]
In some embodiments, at least one ultrasound device is integrated on the semiconductor die and
configured to process data corresponding to the digital signal to perform one or more imaging
functions. Further comprising two signal processing modules. In some embodiments, one or more
imaging functions include apodization, back projection, fast hierarchy back projection,
interpolation range movement or other Fourier resampling techniques, dynamic focus, delay
addition processing, and tomography reprocessing. At least one imaging feature selected from a
group of configurations. In some such embodiments, such performance of the imaging function
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results in the formation of an ultrasound image or results in the formation of an ultrasound
image, and thus, in some embodiments, an integrated super. A sonic imaging device is formed on
the semiconductor die. In at least some embodiments, such features are used to provide
advantageous image types, such as image types that are medically relevant.
[0021]
In some embodiments, the ultrasound device is integrated on the semiconductor die and
configured to process data corresponding to the digital signal to perform one or more back end
processing functions. It further comprises one signal processing module. This may be
advantageous for the reasons previously described. In some embodiments, one or more back-end
processing functions include down-range autofocus, cross-range autofocus, frequency dispersion
compensation, nonlinear apodization, remapping, compression, denoising, compounding,
Doppler, At least one back end processing function selected from the group consisting of
elastography, spectroscopy, and basis tracking.
[0022]
In some embodiments, the ultrasound device further comprises a microprocessor integrated on
the semiconductor die and configured to perform at least one digital signal processing function.
In some embodiments, the microprocessor is configured to reduce the bandwidth of data
corresponding to the digital signal, which in some embodiments further processes the data, as
well as computers, smartphones, and tablets. Are advantageous for facilitating the
communication of data to external components such as In some embodiments, including a
microprocessor on the semiconductor die further facilitates the realization of an integrated
ultrasound device.
[0023]
In some embodiments, the microprocessor is configured to perform one or more imaging
functions. In some embodiments, one or more imaging functions include apodization,
backprojection, fast hierarchy backprojection, interpolation range movement or other Fourier
resampling techniques, dynamic focus, delay-and-sum processing, and tomography imaging And
at least one image forming function selected from the group consisting of
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[0024]
In some embodiments, the microprocessor is configured to perform one or more back end
processing functions. In some embodiments, one or more back-end processing functions include
down-range autofocus, cross-range autofocus, frequency dispersion compensation, nonlinear
apodization, remapping, compression, denoising, compounding, Doppler, At least one back end
processing function selected from the group consisting of elastography, spectroscopy, and basis
tracking.
[0025]
In some embodiments, the device is integrated on a semiconductor die and configured to process
an analog signal and separate the waveform therefrom before the ADC converter converts the
analog signal to a digital signal. , At least one additional component. In some embodiments, at
least one additional component comprises an analog quadrature demodulator, and in some
embodiments comprises an analog dechirp module. Inclusion of such processing circuitry in
some embodiments further facilitates the formation of an integrated ultrasound device that can
be in digital communication with external components.
[0026]
In some embodiments, the ultrasonic transducer element comprises one or more micromachined
ultrasonic transducer cells. In some embodiments, the one or more micromachined ultrasonic
transducer cells comprise one or more capacitive micromachined ultrasonic transducer (CMUT)
cells, and in some embodiments, one Or a plurality of CMOS ultrasonic transducer (CUT) cells.
The use of such a cell, according to some embodiments, facilitates the integration of the
ultrasonic transducer with other components on a CMOS wafer.
[0027]
According to an aspect of the present technology, there is provided a method for processing a
signal from an ultrasonic transducer element, the method using at least one component
integrated on the same semiconductor die as the ultrasonic transducer element. And processing
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the signal corresponding to the output of the transducer element to separate the waveform
therefrom. In some embodiments, such processing reduces the amount of data, which in turn
facilitates the collection and transmission of ultrasound data.
[0028]
In some embodiments, at least one component comprises an analog quadrature demodulator, and
in some embodiments comprises an analog dechirp module. In some embodiments, the ultrasonic
transducer element comprises one or more micromachined ultrasonic transducer cells. In some
embodiments, the one or more micromachined ultrasonic transducer cells comprise one or more
capacitive micromachined ultrasonic transducer (CMUT) cells, and in some embodiments, one Or
a plurality of CMOS ultrasonic transducer (CUT) cells. The use of such a cell, according to some
embodiments, facilitates the integration of the ultrasonic transducer with other components on a
CMOS wafer.
[0029]
According to an aspect of the present technology, an ultrasound device is provided, the
ultrasound device being integrated on a semiconductor die with at least one ultrasonic
transducer element integrated on a semiconductor die, at least one ultra And at least one
component configured to process a signal corresponding to the output of the sonic transducer
element and separate the waveform therefrom. In some embodiments, such configuration of
components facilitates the realization of an integrated ultrasound device. Waveform separation
reduces the amount of data, which in turn facilitates the acquisition and transmission of
ultrasound data.
[0030]
In some embodiments, at least one component comprises an analog quadrature demodulator, and
in some embodiments, at least one component comprises an analog dechirp module. In some
embodiments, the at least one ultrasonic transducer element comprises one or more
micromachined ultrasonic transducer cells. In some embodiments, the one or more
micromachined ultrasonic transducer cells comprise one or more capacitive micromachined
ultrasonic transducer (CMUT) cells, and in some embodiments, one Or a plurality of CMOS
ultrasonic transducer (CUT) cells. The use of such a cell, according to some embodiments,
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facilitates the integration of the ultrasonic transducer with other components on a CMOS wafer.
[0031]
According to an aspect of the present technology, a method is provided for configuring at least
two ultrasonic transducer elements, each comprising a plurality of ultrasonic transducer cells.
The method comprises coupling at least one ultrasonic transducer cell in one of the at least two
ultrasonic transducer elements to at least one ultrasonic transducer cell in the other of the at
least two ultrasonic transducer elements Including. In some embodiments, such coupling
advantageously reduces the grating lobes of the ultrasonic waveform generated by the ultrasonic
transducer element. Additionally, in some embodiments, such coupling facilitates beneficial use
of the entire transducer area.
[0032]
In some embodiments, combining includes coupling at least one ultrasonic transducer cell of one
of the at least two ultrasonic transducer elements and at least one of the other of the at least two
ultrasonic transducer elements. Coupling to the ultrasonic transducer cell via the resistive
element. In some embodiments, the resistive element comprises a polysilicon resistor. The use of
such resistors, and the preferred selection of resistance values, optimizes the performance of the
ultrasonic transducer element in some embodiments.
[0033]
In some embodiments, coupling includes coupling a first pair of ultrasonic transducer cells of
different ones of the at least two ultrasonic transducer elements with a first coupling element
having a first impedance value. Combining and coupling a second pair of ultrasonic transducer
cells of different ones of the at least two ultrasonic transducer elements with a second coupling
element having a second impedance value different from the first impedance value. And
combining. By suitable selection of impedance values, in some embodiments, the performance of
the ultrasonic transducer element is optimized. In some embodiments, combining includes
coupling at least one ultrasonic transducer cell in one of the at least two ultrasonic transducer
elements and at least one other in the other of the at least two ultrasonic transducer elements.
Establishing inductive coupling with the ultrasonic transducer cell.
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[0034]
In some embodiments, the method further comprises mixing at least some of the ultrasonic
transducer cells of the at least two ultrasonic transducer elements.
[0035]
In some embodiments, each of the at least two ultrasonic transducer elements comprises one or
more micromachined ultrasonic transducer cells.
The use of such a cell in accordance with some embodiments facilitates the integration of
ultrasonic transducers with other components on a CMOS wafer.
[0036]
In some embodiments, the method further comprises apodizing at least some transducer cells in
each of the at least two transducer elements. In some embodiments, apodizing comprises
apodizing at least one transducer cell of one of the at least two ultrasonic transducer elements
and at least one transducer cell of the other of the at least two transducer elements. To do.
[0037]
According to aspects of the present technique, an ultrasound device is provided that comprises at
least two ultrasound transducer elements each comprising a plurality of ultrasound transducer
cells. At least one ultrasonic transducer cell in one of the at least two ultrasonic transducer
elements is coupled to at least one ultrasonic transducer cell in the other of the at least two
ultrasonic transducer elements. In some embodiments, such coupling advantageously reduces the
grating lobes of the ultrasonic waveform generated by the ultrasonic transducer element. In
addition, in some embodiments, such coupling facilitates beneficial use of the entire transducer
area.
[0038]
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In some embodiments, at least one transducer cell in one of the at least two ultrasonic transducer
elements is via a resistive element to at least one transducer cell in the other of the at least two
transducer elements. Combined. In some embodiments, the resistive element comprises a
polysilicon resistor.
[0039]
In some embodiments, one of the at least two transducer elements comprises at least first and
second transducer cells, and the other of the at least two transducer elements comprises at least
third and fourth transducer cells. The first transducer cell and the third transducer cell are
coupled through the first coupling element having the first impedance value, and the second
transducer cell and the fourth transducer cell are different from the first impedance value It is
coupled via a second coupling element having a second impedance value. By suitable selection of
impedance values, in some embodiments, the performance of the ultrasonic transducer element
is optimized.
[0040]
In some embodiments, inductive coupling is established between at least one transducer cell in
one of the at least two transducer elements and at least one transducer cell in the other of the at
least two transducer elements. As such, at least two transducer elements are configured and
arranged.
[0041]
In some embodiments, at least some of the transducer cells of the at least two transducer
elements are mixed, and in some embodiments, this provides a benefit in terms of beneficial use
of the transducer element area.
[0042]
In some embodiments, each of the at least two ultrasonic transducer elements comprises one or
more micromachined ultrasonic transducer cells.
The use of such a cell, according to some embodiments, facilitates the integration of the
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ultrasonic transducer with other components on a CMOS wafer.
[0043]
In some embodiments, at least one transducer cell in each of the at least two transducer elements
is apodized.
In some embodiments, at least one transducer cell in one of the at least two ultrasonic transducer
elements and at least one transducer cell in the other of the at least two transducer elements are
apodized.
[0044]
According to an aspect of the present technology, there is provided a method for voltage biasing
an ultrasonic transducer element, wherein the method uses an output of the pulsar to drive the
ultrasonic transducer element, such that the ultrasonic transducer The element includes emitting
an ultrasonic pulse. The pulsar can output a drive signal to one or more transducer elements
corresponding to the generated waveform. Thus, in at least some embodiments, the pulsar is a
circuit suitable for receiving, for example, a waveform from a waveform generator and
generating a pulse (eg, a voltage pulse) to drive an ultrasonic transducer element . In addition, at
least in some cases, the pulsar is not used to drive the ultrasonic transducer element, so that
when the ultrasonic transducer element emits an ultrasonic pulse, the output of the pulsar is
ultrasonically It can be applied as a bias signal to the transducer element. In at least some
embodiments, such operation can be used to provide a safe high voltage bias of the transducer
elements.
[0045]
According to an aspect of the present technology, an ultrasound device is provided, the
ultrasound device coupled to at least one ultrasonic transducer element and at least one
ultrasonic transducer, and in at least some cases at least one transducer. The pulsar output
comprises a pulsar configured and arranged to be used to bias at least one ultrasonic transducer
element when the element is used to sense received ultrasonic energy.
[0046]
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According to an aspect of the present technology, there is provided a method for biasing at least
one ultrasonic transducer element integrated on a semiconductor die, the method comprising at
least using a bias voltage applied to the semiconductor die. Biasing one ultrasonic transducer
element.
In some embodiments, the method grounds at the side of the at least one ultrasonic transducer
element facing the object while the at least one ultrasonic transducer element is used to image or
treat the object. Further comprising applying Such biasing, in some embodiments, provides for
safe operation of the ultrasonic transducer element and minimizes the risk of electrical shock to
the object.
[0047]
According to an aspect of the present technology, an ultrasound device is provided, the
ultrasound device comprising at least one ultrasonic transducer element integrated on a
semiconductor die. At least one ultrasonic transducer element is configured and arranged on the
die such that a bias voltage applied to the die is also used to bias the at least one ultrasonic
transducer element. In at least some embodiments, such an arrangement is used to provide a safe
high voltage bias of the transducer elements.
[0048]
In some embodiments, the ultrasound device is configured to image or treat an object using at
least one ultrasonic transducer element. The side of at least one ultrasonic transducer element
configured to face the object during imaging or treatment is connected to ground, which in some
embodiments is safe by minimizing the risk of electrical shock. Results in In some embodiments,
the at least one ultrasonic transducer element comprises one or more micromachined ultrasonic
transducer cells. In some embodiments, the one or more micromachined ultrasonic transducer
cells comprise one or more capacitive micromachined ultrasonic transducer (CMUT) cells, and in
some embodiments, one Or a plurality of CMOS ultrasonic transducer (CUT) cells. The use of
such a cell, according to some embodiments, facilitates the integration of the ultrasonic
transducer with other components on a CMOS wafer.
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[0049]
According to an aspect of the present technology, there is provided a method for biasing at least
one ultrasonic transducer element, the method wherein at least one ultrasonic transducer
element is used to image or treat an object Meanwhile, applying a ground on the side of the at
least one ultrasonic transducer element facing the object. Such biasing, in some embodiments,
facilitates safe operation of the device by minimizing the risk of electrical shock.
[0050]
According to aspects of the present technology, an ultrasound device is configured to image or
treat an object using at least one ultrasonic transducer element. The side of at least one
ultrasonic transducer element configured to face the object during imaging or treatment is
connected to ground, which in some embodiments is safe by minimizing the risk of electrical
shock. Results in
[0051]
According to an aspect of the present technique, a method is provided for configuring first and
second transmission control circuits in an ultrasound device, each of the first and second
transmission control circuits being of an ultrasonic transducer element. A pulse generator for
driving the pulser, the method comprising: when the first control circuit receives the transmit
enable signal, the first waveform generated by the first waveform generator is the first pulser;
The length of the first delay between when applied is the second waveform generated by the
second waveform generator when the second control circuit receives the transmit enable signal.
Comprising differently configuring the first transmission control circuit and the second
transmission control circuit to be different from the length of the second delay between when
applied to the pulser. In at least some embodiments, such control of the delay achieves beneficial
operations, for example in terms of beneficial ultrasound imaging capabilities.
[0052]
In some embodiments, configuring the first and second transmission control circuits includes
delaying the transmission enable signal by a first length of time before the transmission enable
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signal reaches the first waveform generator. Configuring the first transmit control circuit to be
switched on, and the second transmit enable signal being delayed for a second length of time
before the transmit enable signal reaches the second waveform generator. Configuring the
transmission control circuit of The second length of time is, in some embodiments, different than
the first length of time.
[0053]
In some embodiments, configuring the first and second transmission control circuits comprises
configuring the first waveform generator to have a first start frequency and the second waveform
generator , And having a second start frequency different from the first start frequency. In some
embodiments, configuring the first and second transmission control circuits comprises
configuring the first waveform generator to have a first start phase, and the second waveform
generator , And having a second start phase different from the first start phase. In some
embodiments, configuring the first and second transmission control circuits comprises:
generating a first waveform output by the first waveform generator before the first waveform
reaches the first pulser Configuring the first transmission control circuit such that the waveform
is delayed by a first length of time, and by the second waveform generator before the second
waveform reaches the second pulser Configuring the second transmission control circuit such
that the output second waveform is delayed by a second length of time different from the first
length of time. In at least some embodiments, such control facilitates generating waveforms of
various objects for use in, for example, ultrasound imaging as described herein.
[0054]
According to an aspect of the present technology, an ultrasound device is provided, the
ultrasound device comprising at least first and second ultrasonic transducer elements, a first
transmission control circuit, and a second transmission control circuit. . The first transmission
control circuit is coupled to the first ultrasonic transducer element to drive the first ultrasonic
transducer element, such that the first ultrasonic transducer element emits an ultrasonic pulse.
And a first waveform generator coupled to the first pulser to provide the first pulser with the first
waveform in response to the reception of the transmission enable signal by the first transmission
control circuit. At least one first affecting the length of a first delay between when the first
transmission control circuit receives the transmission enable signal and when the first waveform
is applied to the first pulser; It can contain one component. The second transmission control
circuit is coupled to the second ultrasonic transducer element to drive the second ultrasonic
transducer element, such that the second ultrasonic transducer element emits an ultrasonic
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pulse. A second waveform generator coupled to the second pulser and providing a second
waveform to the second pulser in response to the reception of the transmission enable signal by
the second transmission control circuit; At least one second configuration affecting the length of
the second delay between when the two transmission control circuits receive the enable signal
and when the second waveform is applied to the second pulser And an element. The at least one
first component is configured differently to the at least one second component, such that the
length of the second delay is different than the length of the first delay. In at least some
embodiments, different delays provide beneficial operation, for example, by facilitating the
generation of various desired ultrasound waveforms.
[0055]
In some embodiments, at least one first component delays the enable signal by a first number of
clock cycles before providing the enable signal to the first waveform generator. The at least one
second component delays the enable signal by a second number of clock cycles different from
the first number of clock cycles before providing the enable signal to the second waveform
generator A second shift register is provided. In some embodiments, the at least one first
component includes a first register that includes a first value that determines the start frequency
of the first waveform generator, the at least one second component Includes a second register
that includes a second value different from the first value that determines the start frequency of
the second waveform generator. In some embodiments, the at least one first component includes
a first register including a first value that determines a start phase of the first waveform
generator, the at least one second component And a second register that includes a second value
different from the first value that determines the start phase of the second waveform generator.
In some embodiments, at least one first component is configured to generate a first waveform
output by the first waveform generator before the first waveform reaches the first pulser. A first
delay element delaying by a length of time, at least one second component being output by the
second waveform generator before the second waveform reaches the second pulser A second
delay element is provided for delaying the second waveform by a second length of time different
from the first length of time. In at least some embodiments, such an arrangement facilitates the
generation of various useful ultrasound waveforms, for example by allowing control of waveform
parameters.
[0056]
According to an aspect of the present technology, there is provided a method for configuring at
least first and second waveform generators, the method comprising: first and second
11-04-2019
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configurable of at least first and second waveform generators Including using the controller to
control the value of the operating parameter. In at least some embodiments, such control allows
the waveform generator to be programmable, such that the waveform generator is programmed
or controlled to provide the desired waveform, for example by controlling waveform parameters.
Can.
[0057]
In some embodiments, a method includes generating a series of event numbers at a controller
and, for a first waveform generator, an event provided by the controller from a first memory
associated with a first waveform generator. The method further includes retrieving a first value
associated with the number and providing the first value to the first waveform generator for use
as the first configurable operating parameter. The method comprises, for a second waveform
generator, retrieving a second value related to the number of events provided by the controller
from a second memory associated with the second waveform generator, and a second
configurable Providing the second value to the second waveform generator for use as an
operating parameter. In this manner, in at least some embodiments, control of the waveform
generated by the waveform generator can be achieved, and a desired (e.g., medically relevant)
ultrasound waveform can be generated.
[0058]
In some embodiments, the first and second configurable operating parameters control the same
functionality of the first and second waveform generators. For at least one event number, the first
and second values retrieved from the first and second memories are different.
[0059]
In some embodiments, the method further includes using a controller to transmit an enable
signal to each of the first and second waveform generators. In some embodiments, the method
sets each of the first configurable operating parameter of the first waveform generator and the
second configurable operating parameter of the second waveform generator to have different
values. Further include. In this manner, in some embodiments, different waveforms can be
generated by different waveform generators that can be used, for example, to achieve the desired
ultrasound waveform generation in ultrasound imaging.
11-04-2019
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[0060]
According to an aspect of the present technology, a device is provided, the device configured to
generate waveforms for transmission by at least first and second corresponding ultrasonic
transducer elements. A waveform generator, wherein the first waveform generator includes at
least one first configurable operating parameter, and the second waveform generator includes at
least one second configurable operating parameter. A second waveform generator and a
controller configured to control the values of the first and second configurable operational
parameters. In this manner, the desired configurability of the waveform produced by the
waveform generator is achieved in some embodiments.
[0061]
In some embodiments, the controller is configured to output a series of transmit event numbers.
In some embodiments, the first waveform generator is associated with a first event memory that
stores values for first configurable operational parameters associated with respective transmit
event numbers and transmitted from the controller The event number is received and configured
to output a corresponding stored value for the first configurable operating parameter for use
thereby by the first waveform generator. In some embodiments, the second waveform generator
is associated with a second event memory that stores values for a second configurable
operational parameter associated with the respective number of transmit events, transmitted
from the controller The event number is received and configured to output a corresponding
stored value for the second configurable operating parameter for use thereby by the second
waveform generator. In this manner, in some embodiments, the waveforms generated by the
waveform generator can be controlled, for example, to achieve the desired waveform when
performing ultrasound imaging.
[0062]
In some embodiments, for at least one event number output by the controller, the first event
memory and the second event memory store different associated values for the first and second
configurable operating parameters. .
[0063]
In some embodiments, the controller is further configured to communicate a transmit enable
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20
signal to each of the first and second waveform generators.
[0064]
In some embodiments, the first configurable operating parameter may be set to a different value
than the second configurable operating parameter.
[0065]
According to an aspect of the present technology, a method is provided for making an ultrasound
device, the method comprising integrating digital receiving circuitry on the same semiconductor
die as at least one CMOS ultrasonic transducer element.
The digital receiving circuit may be a digital circuit configured to receive a signal from an
ultrasonic transducer cell or element.
Examples are described herein.
In some embodiments, such an arrangement provides, or otherwise facilitates, an integrated
ultrasound device by allowing the ultrasonic transducer and digital circuitry to be on the same
semiconductor die. Can. A small ultrasound device provides several embodiments. Digital
circuitry also facilitates digital communication with external components in some embodiments,
such as external computers, smart phones, tablets, or other processing components.
[0066]
According to an aspect of the present technology, a device is provided, the device comprising at
least one CMOS ultrasonic transducer element and digital receiving circuit formed on a single
integrated circuit substrate. In some embodiments, such an arrangement provides or otherwise
facilitates an integrated ultrasound device by allowing the ultrasonic transducer and digital
circuitry to be on the same semiconductor die. A small ultrasound device provides several
embodiments. Digital circuitry also facilitates digital communication with external components in
some embodiments, such as external computers, smart phones, tablets, or other processing
components.
11-04-2019
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[0067]
According to an aspect of the present technology, there is provided a method for making an
ultrasound device, the method comprising: at least first and second transmission control circuits
and at least first corresponding to the first and second ultrasonic transducer elements. And
manufacturing the at least first and second ultrasonic transducer elements on a CMOS circuit
(e.g., on a higher or later provided processing layer) comprising the second reception control
circuit. In at least some embodiments, such manufacturing facilitates the formation of an
integrated ultrasound device that includes an ultrasonic transducer and associated circuitry. Also,
the device can be compact due at least in part to the placement of the ultrasonic transducer in
the circuit as described.
[0068]
In some embodiments, each of the first and second receive control circuits comprises an analog
to digital converter, and in some embodiments further comprises digital signal processing
circuits. The inclusion of digital circuitry facilitates data processing and digital communication
with external components in some embodiments.
[0069]
In some embodiments, at least first and second ultrasonic transducer elements are fabricated on
top of the CMOS circuitry (e.g., above the processing layer provided higher or later), so that the
first The transmission control circuit and the first reception control circuit are both disposed
under the first ultrasonic transducer element, and the second transmission control circuit and the
second reception control circuit are both arranged in the second ultrasonic It is disposed below
the transducer element. In some embodiments, the circuit components may be under the
ultrasonic transducers in the sense that the circuit components can be fabricated on processing
layers that are completed prior to formation of the ultrasonic transducers. In some embodiments,
the ultrasonic transducer is closer to the device side of the substrate (eg, semiconductor
substrate) than the circuit. In at least some embodiments, such an arrangement allows for the
fabrication of a miniature ultrasound device.
11-04-2019
22
[0070]
In some embodiments, manufacturing at least first and second ultrasonic transducer elements
includes manufacturing at least first and second ultrasonic transducer elements on the same
semiconductor substrate as the CMOS circuit. In some embodiments, producing at least first and
second ultrasonic transducer elements is a first waveform coupled to drive a first pulser for the
first ultrasonic transducer elements. Manufacturing a first transmission control circuit to include
a generator, and a second waveform generator coupled to drive a second pulser for a second
ultrasonic transducer element Manufacturing the second transmission control circuit. An
integrated ultrasound device, in some embodiments, is achieved including signal generation
functionality on a semiconductor substrate.
[0071]
According to an aspect of the present technology, an ultrasound device is provided, the
ultrasound device being disposed below at least first and second ultrasonic transducer elements
and at least first and second ultrasonic transducer elements And a CMOS circuit. The CMOS
circuit integrates therein first and second transmission control circuits corresponding to the first
and second ultrasonic transducer elements and first and second reception control circuits. In at
least some embodiments, such an arrangement facilitates the formation of an integrated
ultrasound device that includes an ultrasonic transducer and associated circuitry. The device can
be compact due at least in part to placing the ultrasonic transducer with respect to the circuit as
described.
[0072]
In some embodiments, each of the first and second receive control circuits comprises an analog
to digital converter. In some embodiments, each of the first and second receive control circuitry
further comprises digital signal processing circuitry. The inclusion of digital circuitry facilitates
data processing and digital communication with external components in some embodiments.
[0073]
In some embodiments, the first transmission control circuit and the first reception control circuit
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23
are both disposed below the first ultrasonic transducer element, and the second transmission
control circuit and the second reception control The circuits are both disposed below the second
ultrasonic transducer element. In some embodiments, such an arrangement allows for the
fabrication of a miniature ultrasound device.
[0074]
In some embodiments, the first and second ultrasonic transducer elements are integrated on the
same semiconductor die as the CMOS circuitry, thereby producing an integrated ultrasound
device in at least some embodiments. Will be ready.
[0075]
In some embodiments, the first transmission control circuit comprises a first waveform generator
coupled to drive a first pulser for a first ultrasonic transducer element, the second transmission A
control circuit comprises a second waveform generator coupled to drive a second pulser for a
second ultrasonic transducer element.
[0076]
In some embodiments, each of the first and second ultrasonic transducer elements comprises one
or more micromachined ultrasonic transducer cells.
In some embodiments, the one or more micromachined ultrasonic transducer cells comprise one
or more capacitive micromachined ultrasonic transducer (CMUT) cells, and in some
embodiments, one Alternatively, the plurality of micromachined ultrasonic transducer cells
comprise one or more CMOS ultrasonic transducer (CUT) cells.
The use of such a cell, according to some embodiments, facilitates the integration of the
ultrasonic transducer with other components on a CMOS wafer.
[0077]
According to an aspect of the present technology, there is provided a method for processing a
signal from an ultrasonic transducer element, the method comprising: using the component
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24
integrated on the same semiconductor die as the ultrasonic transducer element; Transmitting the
data corresponding to the output of the ultrasonic transducer element from A as a high speed
serial data stream. Such operations in some embodiments facilitate communication of data to
external processing components such as computers, smartphones, and tablets.
[0078]
In some embodiments, the method comprises converting an analog signal corresponding to the
output of the ultrasonic transducer element into a digital signal and transmitting data
corresponding to the digital signal from the semiconductor die as a high speed serial data stream
And transmitting the included data. Digital communication with external components is
implemented in some embodiments.
[0079]
In some embodiments, the method further includes processing the digital signal to reduce its
data bandwidth using at least one additional component integrated on the semiconductor die,
which In some embodiments, it is advantageous to facilitate further processing of the data as well
as communication of the data to external components such as computers, smart phones, and
tablets. In some embodiments, the at least one additional component comprises a digital
quadrature demodulator. In some embodiments, the at least one additional component comprises
an averaging module. In some embodiments, the at least one additional component comprises a
matched filter, and in alternative embodiments comprises a mismatched filter. In some
embodiments, the at least one additional component comprises a finite impulse response (FIR)
filter. In some embodiments, the at least one additional component comprises a half band
decimation low pass filter. In some embodiments, the at least one additional component
comprises a dechirp module.
[0080]
In some embodiments, the method processes the analog signal from the waveform prior to
converting the analog signal to a digital signal using at least one additional component integrated
on the semiconductor die It further includes separating. In some embodiments, such processing
reduces the amount of data, which in turn facilitates the collection and transmission of
ultrasound data. In some embodiments, at least one additional component comprises an analog
11-04-2019
25
quadrature demodulator, and in some embodiments comprises an analog dechirp module.
[0081]
In some embodiments, transmitting comprises transmitting data corresponding to the output of
the ultrasonic transducer element from the semiconductor die as a high speed serial data stream
using a USB module. In some embodiments, the USB module comprises a USB 3.0 module. In
some embodiments, transmitting comprises transmitting data corresponding to the output of the
ultrasonic transducer element from the semiconductor die using a low voltage differential signal
(LVDS) link. Such communication protocols facilitate the use of ultrasonic transducer elements
with external components.
[0082]
According to an aspect of the present technology, an ultrasound device is provided, the
ultrasound device being integrated on a semiconductor die with at least one ultrasonic
transducer element integrated on the semiconductor die, from the semiconductor die And a high
speed serial data module configured to transmit data corresponding to the output of the
ultrasonic transducer element as a high speed serial data stream. The high speed serial data
stream facilitates the use of the ultrasound device with respect to devices capable of receiving
the serial data stream in some embodiments.
[0083]
In some embodiments, the device further comprises an analog-to-digital (ADC) converter
integrated on the semiconductor die and configured to convert an analog signal corresponding to
the output of the ultrasonic transducer element into a digital signal. Prepare. In some
embodiments, the high speed serial data module is configured to transmit data corresponding to
digital signals from the semiconductor die as a high speed serial data stream. In some
embodiments, such an operation facilitates communication of ultrasound data with an external
device.
[0084]
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26
In some embodiments, the ultrasound device further comprises at least one signal processing
module integrated on the semiconductor die and configured to process the digital signal to
reduce its data bandwidth, Is, in some embodiments, advantageous to facilitate further
processing and communication to external components such as computers, smartphones, and
tablets. In some embodiments, at least one signal processing module comprises a digital
quadrature demodulator. In some embodiments, at least one signal processing module comprises
an averaging module. In some embodiments, the at least one signal processing module comprises
a matched filter, and in alternative embodiments comprises a mismatched filter. In some
embodiments, at least one signal processing module comprises a finite impulse response filter. In
some embodiments, the at least one signal processing module comprises a half band decimation
low pass filter. In some embodiments, at least one signal processing module comprises a
dechirping module.
[0085]
In some embodiments, the device is integrated on a semiconductor die and configured to process
an analog signal and separate the waveform therefrom before the ADC converter converts the
analog signal to a digital signal. , At least one additional component. In some embodiments, at
least one additional component comprises an analog quadrature demodulator, and in some
embodiments comprises an analog dechirp module.
[0086]
In some embodiments, the high speed serial data module comprises a USB module. In some
embodiments, the USB module comprises a USB 3.0 module. In some embodiments, the high
speed serial data module comprises a low voltage differential signal (LVDS) link module. The use
of such a communication protocol facilitates the use of ultrasound devices in external
components.
[0087]
According to aspects of the present technique, the transmission and / or control circuitry for at
least first and second ultrasonic transducer elements integrated on the same semiconductor die
as the transmission and / or control circuitry is provided. A method is provided for operating the
11-04-2019
27
at least one first ultrasonic transducer element and the at least one second ultrasonic transducer
element using the controller to control values of operating parameters of the transmission and /
or control circuit. Including. In at least some embodiments, such control facilitates generation of
the desired waveform in some embodiments.
[0088]
In some embodiments, the method further includes communicating the operating parameters to a
register associated with the transmit and / or control circuit via the high speed serial data link
with a controller that is not integrated on the semiconductor die.
[0089]
In some embodiments, using the controller controls values of operating parameters of the
waveform generator of the transmission control circuit for the at least first and second ultrasonic
transducer elements using the controller Including.
In some embodiments, using the controller controls the value of operating parameters of the
receiver control circuit amplifier for the at least first and second ultrasonic transducer elements
using the controller. Including.
[0090]
According to an aspect of the present technology, a device is provided, the device being
integrated on a semiconductor die with at least first and second ultrasonic transducer elements
integrated on a semiconductor die Or a control circuit and a controller configured to control the
values of operating parameters of the transmission and / or control circuit for at least the first
and second ultrasonic transducer elements. In some embodiments, such a configuration
represents at least a portion of an integrated ultrasound device, such as an ultrasound imaging
device configured to collect ultrasound data suitable for forming an ultrasound image. .
[0091]
In some embodiments, the controller is not integrated on the semiconductor die and is
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configured to communicate the operating parameters to the registers associated with the
transmit and / or control circuitry via the high speed serial data link. In some embodiments, the
controller is configured to control the value of operating parameters of the waveform generator
of the transmission control circuit for at least the first and second ultrasonic transducer
elements. In some embodiments, the controller is configured to control the value of operating
parameters of the receiver control circuit amplifier for at least the first and second ultrasonic
transducer elements.
[0092]
According to an aspect of the present technology, a device is provided that comprises an
ultrasound imaging chip and a high intensity focused ultrasound (HIFU) chip. The ultrasound
imaging chip and the HIFU chip are combined and work in combination to perform the image
guided HIFU. The ultrasound imaging chip includes suitable components (e.g., ultrasonic
transducers and circuits) and can collect ultrasound data suitable for forming an ultrasound
image. The HIFU chip contains suitable components (eg, ultrasonic transducers and circuits) and
can apply HIFU energy. In some embodiments, an image resulting from ultrasound data collected
by ultrasound imaging is used to direct the application of HIFU by the HIFU chip.
[0093]
According to an aspect of the present technology, a device is provided that comprises an
ultrasound imaging circuit and a high intensity focused ultrasound (HIFU) circuit integrated into
a single chip. The device is configured to perform an image guidance HIFU. Thus, in some
embodiments, a single device is configured to perform multiple ultrasound functions.
[0094]
According to an aspect of the present technology, a device is provided, the arrangement of an
ultrasonic transducer element on a CMOS wafer, an integrated circuit formed on the CMOS wafer
and electrically coupled to the arrangement of the ultrasonic transducer element. Prepare. The
integrated circuit is configured to drive voltages up to about 50V. Such voltages are
advantageous for the application of HIFU and / or the implementation of ultrasound imaging,
which in some embodiments may require the use of high voltages.
11-04-2019
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[0095]
In some embodiments, the integrated circuit comprises submicron nodes. The submicron nodes
are configured to drive voltages up to about 50V. In some embodiments, sub-micron nodes may
refer to nodes that are less than about 1 micron. In some embodiments, deep sub-micron nodes
may refer to nodes that are less than about 0.3 microns. In some embodiments, an ultra deep
sub-micron node may refer to a node that is less than about 0.1 microns. Thus, a compact
integrated ultrasound device capable of maintaining high voltages useful in some ultrasound
applications is provided in at least some embodiments.
[0096]
In at least some of the embodiments described herein where ultrasonic transducer elements are
provided or used, the ultrasonic transducer elements comprise one or more micromachined
ultrasonic transducer cells be able to. In some embodiments, the one or more micromachined
ultrasonic transducer cells comprise one or more capacitive micromachined ultrasonic
transducer (CMUT) cells, and in some embodiments, one Or a plurality of CMOS ultrasonic
transducer (CUT) cells.
[0097]
Various aspects and embodiments of the disclosed technology will be described with reference to
the following figures. It should be understood that the figures are not necessarily to scale. Items
appearing in more than one figure are indicated by the same reference numeral in all the figures
in which the item appears.
[0098]
FIG. 7 illustrates an illustrative example of a monolithic ultrasound device embodying various
aspects of the present invention.
[0099]
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30
FIG. 7 illustrates an exemplary implementation of an imaging device adapted to transmit acoustic
signals and receive only backscattered pulses from an object. FIG. 7 illustrates an exemplary
implementation of an imaging device adapted to transmit acoustic signals and receive only
backscattered pulses from an object.
[0100]
FIG. 1 illustrates an exemplary implementation of a system for imaging an object employing a
pair of opposing imaging devices. FIG. 1 illustrates an exemplary implementation of a system for
imaging an object employing a pair of opposing imaging devices.
[0101]
FIG. 6 shows an illustrative example of how individual transducer elements in a transducer array
can be arranged with respect to the CMOS circuitry for that element.
[0102]
FIG. 7 shows an illustrative example of an ultrasound unit comprising groups of individual
ultrasound devices that can operate together under the direction of a controller.
[0103]
FIG. 7 illustrates how a single transducer element can fit within a larger transducer array in some
embodiments.
[0104]
FIG. 6 illustrates one of five different examples of how a given transducer element in an array
may be configured in some embodiments. FIG. 6 illustrates one of five different examples of how
a given transducer element in an array may be configured in some embodiments. FIG. 6
illustrates one of five different examples of how a given transducer element in an array may be
configured in some embodiments. FIG. 6 illustrates one of five different examples of how a given
transducer element in an array may be configured in some embodiments. FIG. 6 illustrates one of
five different examples of how a given transducer element in an array may be configured in some
embodiments.
[0105]
FIG. 7 illustrates an example of how transducer elements can be mixed in some embodiments to
reduce grating lobes and the like. FIG. 7 illustrates an example of how transducer elements can
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be mixed in some embodiments to reduce grating lobes and the like. FIG. 7 illustrates an example
of how transducer elements can be mixed in some embodiments to reduce grating lobes and the
like.
[0106]
FIG. 6 illustrates an example of how transducer cells included in each transducer element of an
array may be coupled to one another in some embodiments to reduce grating lobes and the like.
FIG. 6 illustrates an example of how transducer cells included in each transducer element of an
array may be coupled to one another in some embodiments to reduce grating lobes and the like.
[0107]
In some embodiments, how can the TX control circuit and RX control circuit for a given
transducer element be used to energize the element to emit an ultrasonic pulse, or FIG. 6 is a
block diagram illustrating whether signals from elements representing detected ultrasonic pulses
can be received and processed.
[0108]
FIG. 5 illustrates an embodiment of an ultrasound device in which digital processing of the
received signal may be performed off-chip.
[0109]
FIG. 7 illustrates an embodiment of an ultrasound device in which some or all of the waveform
generator and other digital circuitry may be arranged off-chip.
[0110]
FIG. 6 illustrates an example of circuitry that can be included in each TX control circuit in some
embodiments to allow real time delay and amplification control at any transmit position of the
transducer array. FIG. 6 illustrates an example of circuitry that can be included in each TX
control circuit in some embodiments to allow real time delay and amplification control at any
transmit position of the transducer array.
[0111]
An illustrative example of timing and control circuitry and components that can be employed in
each TX control circuitry to selectively determine values for the registers used by the waveform
generator in the embodiments of FIGS. 12A-12B FIG.
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[0112]
FIG. 5 illustrates an example of components that can be used to selectively determine values for
one or more of the TX control circuitry and / or the operating parameters used by the RX control
circuitry.
[0113]
In some embodiments, an example of inputs and outputs for an event controller of a timing and
control circuit that can be provided to control both transmit and receive events occurring in an
ultrasound device is there.
[0114]
FIG. 15 illustrates an illustrative example of a routine that may be implemented by the event
controller shown in FIG. 14 to generate a preferred set of outputs for controlling transmit and /
or receive events.
[0115]
An illustrative example of a routine that can be employed in connection with the embodiment of
FIG. 13A to selectively determine values for one or more operating parameters used by the TX
control circuit and / or the RX control circuit FIG.
[0116]
FIG. 7 illustrates an alternative implementation of an ultrasound device in which a single
waveform generator can be shared by more than one TX control circuit.
[0117]
FIG. 11 illustrates an illustrative example of components that may be included within the analog
and digital processing blocks of the RX control circuit shown in FIG. 10. FIG. 11 illustrates an
illustrative example of components that may be included within the analog and digital processing
blocks of the RX control circuit shown in FIG. 10.
[0118]
FIG. 2 illustrates an exemplary implementation of the timing and control circuit shown in FIG.
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33
[0119]
FIG. 20 shows an exemplary implementation of the clock generation circuit shown in FIG.
[0120]
FIG. 11 illustrates an illustrative example of components that may be included in the multiplexed
digital processing block of the signal conditioning / processing circuit shown in FIG. FIG. 11
illustrates an illustrative example of components that may be included within the analog and
digital processing blocks of the RX control circuit shown in FIG. 10. FIG. 11 illustrates an
illustrative example of components that may be included within the analog and digital processing
blocks of the RX control circuit shown in FIG. 10. FIG. 11 illustrates an illustrative example of
components that may be included within the analog and digital processing blocks of the RX
control circuit shown in FIG. 10. FIG. 11 illustrates an illustrative example of components that
may be included within the analog and digital processing blocks of the RX control circuit shown
in FIG. 10. FIG. 11 illustrates an illustrative example of components that may be included within
the analog and digital processing blocks of the RX control circuit shown in FIG. 10. FIG. 11
illustrates an illustrative example of components that may be included within the analog and
digital processing blocks of the RX control circuit shown in FIG. 10. FIG. 11 illustrates an
illustrative example of components that may be included within the analog and digital processing
blocks of the RX control circuit shown in FIG. 10.
[0121]
FIG. 6 illustrates an example of a technique for biasing transducer elements in an array or other
arrangement. FIG. 6 illustrates an example of a technique for biasing transducer elements in an
array or other arrangement.
[0122]
FIG. 11 illustrates an example of components that may be included in the multiplexed digital
processing block of the signal conditioning / processing circuit shown in FIG.
[0123]
FIG. 6 illustrates an embodiment where some or all of the waveform removal circuitry and / or
software, imaging circuitry and / or software, and / or back end processing circuitry and / or
software may be located off-chip. FIG. 6 illustrates an embodiment where some or all of the
waveform removal circuitry and / or software, imaging circuitry and / or software, and / or back
end processing circuitry and / or software may be located off-chip.
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[0124]
FIG. 7 illustrates an example of a high voltage NMOS and PMOS layout that can be used in some
embodiments.
[0125]
FIG. 7 illustrates an example of a layout of ultra high voltage NMOS and PMOS that can be used
in some embodiments.
[0126]
FIG. 5 illustrates an example of a high voltage NMOS and PMOS bi-directional or cascode layout
that can be used in some embodiments.
[0127]
FIG. 7 illustrates an example of a high voltage NMOS and PMOS bi-directional or cascode layout
that can be used in some embodiments.
[0128]
FIG. 7 illustrates an example of a pulsar using high voltage NMOS and PMOS layout with high
voltage switches that can be used in some embodiments.
[0129]
FIG. 7 illustrates an example of a dual voltage pulse driver that can be used in some
embodiments. FIG. 7 illustrates an example of a quadruple voltage pulse driver that can be used
in some embodiments.
[0130]
FIG. 6 illustrates an example of a pulsar that does not employ a receive isolation switch that can
be used in some embodiments. FIG. 6 illustrates an example of a pulsar that does not employ a
receive isolation switch that can be used in some embodiments.
[0131]
FIG. 7 illustrates an example of a time interleaved single slope analog to digital converter (ADC),
which may be employed in some embodiments as one or more of the ADC reference values. FIG.
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7 illustrates an example of the operation of a time interleaved single slope analog to digital
converter (ADC), which may be employed in some embodiments as one or more of the ADC
reference values. .
[0132]
FIG. 5 illustrates an example of a time interleaved sample and hold circuit that may be employed
in some embodiments.
[0133]
FIG. 7 illustrates an example of a time-shared high speed ADC that may be employed in some
embodiments as one or more of the ADCs referred to herein. FIG. 7 illustrates an example of
operation of a time-division high speed ADC that may be employed in some embodiments as one
or more of the ADCs referred to herein.
[0099] [0134] Some embodiments of the present disclosure provide novel devices, systems, and
methods that leverage the benefits of CMUT technology and drive the state of the art of
ultrasonic imaging processing in ultrasonic scanners. In some embodiments, a robust and highly
integrated ultrasound "system-on-chip" is directly integrated with an ultrasonic transducer array
manufactured on the same die as a full digital ultrasound front end Provided. According to some
aspects of the present disclosure, this architecture allows for full access to fully digitized channel
data and is a state of the art off-the-shelf computing platform for implementing advanced
imaging algorithms. You can allow the use.
[0100] [0135] Previous efforts in this area have tightly integrated the standard ultrasound
architecture by designing an ASIC that can perform standard beamforming rather than more
advanced techniques. Or focused on the implementation of advanced imaging techniques,
typically techniques that create expensive devices that lack scalable integration techniques. The
present disclosure addresses both of these issues by providing a unique, cost effective, and
scalable integrated ultrasound platform on chip that is sufficiently robust for advanced imaging
applications.
[0101] [0136] Moving beyond standard beamforming methods requires an architecture that can
support more than just transmission of time delayed pulses. Flexibility sufficient to implement
advanced waveform coding techniques requires dedicated system resources for each element in
the transducer array. The present disclosure overcomes this limitation, for example, with a novel
waveform generator. In some embodiments, the integrated circuit uniquely enables this
11-04-2019
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waveform generator to control multi-level (eg, three or more levels) pulsars, in a complete
integrated transducer / CMOS configuration It provides the ability to implement many advanced
ultrasound techniques in subsequent processing, a feature not previously achieved.
[0102] [0137] Often, ultrasound receiver architectures need to reduce data bandwidth from
multiple channels. One way to do this with conventional ultrasound is to use a standard
beamforming method. This operation is irreversible and not compatible with many more
advanced ultrasound imaging reconstruction techniques. In many cases, the data rate of all
channels can exceed the bandwidth of the system's external digital link. Some embodiments
disclosed herein provide a novel architecture that provides the flexibility to use data of all
channels in a manner that allows for an unprecedented level of control data rate for data leaving
the chip. adopt.
[0103] [0138] The integrated circuits detailed herein are uniquely designed for integrated
ultrasound imaging devices. CMOS contacts facilitate direct wafer bonding, sacrificial release, flip
chip bonding, and / or other techniques for establishing interconnections to ultrasound
transducer elements.
[0104] [0139] The aspects and embodiments described above as well as additional aspects and
embodiments are further described below. These aspects and / or embodiments may be used
separately, all together, or any combination of two or more, as the present disclosure is not
limited in this regard.
[0105] [0140] FIG. 1 shows an illustrative example of a monolithic ultrasound device 100
embodying various aspects of the present invention. As shown, device 100 includes one or more
transducer arrangements (eg, arrays) 102, transmit (TX) control circuitry 104, receive (RX)
control circuitry 106, timing and control circuitry 108, signal conditioning / processing circuitry.
110, power management circuitry 118, and / or high intensity focused ultrasound (HIFU)
controller 120 may be included. In the illustrated embodiment, all of the illustrated components
are formed on a single semiconductor die 112. However, it should be understood that in
alternative embodiments, one or more of the illustrated elements may instead be arranged off
chip, as discussed in more detail below. Additionally, although the illustrated example shows both
TX control circuit 104 and RX control circuit 106, in alternative embodiments (also discussed in
more detail below), only TX control circuit or only RX control circuit Can be adopted. For
example, such embodiments use one or more transmit-only devices 100 to transmit acoustic
signals, and one or more receive-only devices 100 to be used to ultrasonically imaged objects.
May be employed in an environment that receives an acoustic signal transmitted through or
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reflected by an object.
[0106] [0141] It should be understood that communication between one or more of the
illustrated components can be implemented in any of numerous ways. In some embodiments,
high-speed in-chip communication, or one or more, using one or more high-speed buses (not
shown), such as, for example, those employed by a unified northbridge. Communication with offchip components can be enabled.
[0107] [0142] The one or more transducer arrangements 102 can take any of many forms, and
aspects of the present technology need not necessarily use any particular type or arrangement of
transducer cells or transducer elements. Absent. Indeed, although the term "array" is used in this
description, in some embodiments, the transducer elements may not be organized in an array
and may instead be arranged in some non-array fashion I want you to understand. In various
embodiments, each of the transducer elements in the array 102 may be, for example, one or
more CMUTs, one or more CMOS ultrasonic transducers (CUTs), and / or one or more other
suitable An ultrasonic transducer cell can be included. In some embodiments, the transducer
element 304 of each transducer array 102 can be formed on the same chip as the electronic
circuitry of the TX control circuit 104 and / or the RX control circuit 106. Many examples of
ultrasonic transducer cells, elements, and arrangements (eg, arrangements), and methods of
integrating such devices underlying CMOS circuits are incorporated herein by reference in their
entirety. No. 61/794, filed on March 15, 2013, entitled "COMPLEMENTARY METAL OXIDE
SEMICONDUCTORS (CMOS) ULTRASONIC TRANSDUCTORS AND METHODS FOR FORMING THE
SAME" and having Attorney Docket No. B1348.70007US00, filed on March 15, 2013 No. 744,
which is discussed in detail.
[0108] [0143] The CUT includes, for example, a cavity formed in a CMOS wafer, with the film
over the cavity and in some embodiments sealing the cavity. Electrodes can be provided to form
the transducer cell from the cavity structure to be covered. A CMOS wafer can include integrated
circuits to which transducer cells can be connected. The transducer cell and the CMOS wafer can
be monolithically integrated, thus forming an integrated ultrasonic transducer cell and integrated
circuit on a single substrate (CMOS wafer).
[0109] [0144] TX control circuit 104 (if included) may be, for example, an individual element of
transducer array 102 or one or more groups of elements within transducer array 102 to
generate an acoustic signal used for imaging. Can be generated to drive the The RX control
circuit 106 (if included) may, on the other hand, receive and process the electrical signals
generated by the individual elements of the transducer array 102 when the acoustic signal
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strikes such elements.
[0110] [0145] In some embodiments, timing and control circuitry 108 serves to generate, for
example, all timing and control signals used to synchronously coordinate the operation of other
elements in device 100. Can. In the example shown, the timing and control circuit 108 is driven
by a single clock signal CLK provided to the input port 116. Clock signal CLK may be, for
example, a high frequency clock used to drive one or more of the on-chip circuit components. In
some embodiments, clock signal CLK is, for example, 1.5625 GHz or 2.5 GHz used to drive a high
speed serial output device (not shown in FIG. 1) in signal conditioning / processing circuit 110.
The clock or other 20 MHz or 40 MHz clock used to drive other digital components on the die
112, and the timing and control circuitry 108, as needed, may operate on the other components
on the die 112. The clock CLK may be divided or multiplied to drive. In other embodiments, two
or more clocks of different frequencies (such as those referenced above) can be separately
supplied to the timing & control circuit 108 from an off-chip source. An illustrative example of a
suitable clock generation circuit 1904 that can be included in the timing and control circuit 108
is discussed below with respect to FIGS. 19 and 20.
[0111] [0146] Power management circuit 118, for example, converts one or more input voltages
VIN from an off-chip source to voltages needed to perform chip operations, otherwise managing
power consumption within device 100. Can play a role in In some embodiments, for example, a
single voltage (eg, 12 V, 80 V, 100 V, 120 V, etc.) can be supplied to the chip, and the power
management circuit 118 optionally uses a charge pump circuit. The voltage can be stepped up or
down through or some other DC-DC voltage conversion mechanism. In other embodiments,
multiple different voltages may be separately provided to power management circuit 118 for
processing and / or distribution to other on-chip components.
[0112] [0147] As shown in FIG. 1, in some embodiments, HIFU controller 120 may be placed on
die 112 to enable generation of HIFU signals through one or more elements of transducer array
102. It can be integrated. In other embodiments, the HIFU controller for driving the transducer
array 102 can be located off chip, or even in a separate device from the device 100. That is,
aspects of the present disclosure relate to providing an ultrasound on-chip HIFU system with and
without ultrasound imaging capabilities. However, it should be understood that some
embodiments may not have HIFU capabilities, and thus may not include the HIFU controller 120.
[0113] [0148] Furthermore, it should be understood that in those embodiments providing HIFU
functionality, HIFU controller 120 may not exhibit a clean circuit. For example, in some
embodiments, the remaining circuitry of FIG. 1 (other than HIFU controller 120) may be suitable
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for providing ultrasound imaging functionality and / or HIFU, ie, some embodiments The same
shared circuit can then operate as an imaging system and / or for HIFU. Whether imaging or
HIFU functionality is exerted may depend on the power provided to the system. HIFUs typically
operate at higher power than ultrasound imaging. Thus, by providing the system with a first
power level (or voltage) suitable for imaging applications, the system can be operated as an
imaging system while providing a higher power level (or voltage) The system can be operated for
HIFU. Such power management can be implemented by off-chip control circuitry in some
embodiments.
[0114] [0149] In addition to using different power levels, imaging and HIFU applications can
utilize different waveforms. Thus, waveform generation circuitry can be used to provide suitable
waveforms for operating the system as either an imaging system or a HIFU system.
[0115] [0150] In some embodiments, the system can operate as both an imaging system and a
HIFU system (eg, capable of implementing image guided HIFU). In some such embodiments, the
same on-chip circuitry can be used to implement both functions, and a suitable timing sequence
is used to control the operation between the two modalities. Further details regarding HIFU
implementations and operational features that may be employed in the various embodiments
described in the present disclosure are incorporated herein by reference in their entirety.
"TRANSMISSIVE IMAGING AND RELATED APPARATUS AND METHODS" And are described in copending and co-owned US patent application Ser. No. 13 / 654,337, filed Oct. 17, 2012.
[0116] [0151] In the illustrated example, one or more output ports 114 can output a high speed
serial data stream generated by one or more components of signal conditioning and processing
circuit 110. Such data streams may be generated, for example, by one or more USB 3.0 modules
and / or one or more 10 GB, 40 GB or 100 GB Ethernet modules integrated on a die 112 . In
some embodiments, the signal stream produced on output port 114 can be sent to a computer,
tablet, or smartphone for generation and / or display of two-dimensional, three-dimensional, and
/ or tomographic images. . In embodiments where the imaging capabilities are incorporated into
the signal conditioning / processing circuit 110 (as further described below), a smartphone or
only with a limited amount of processing power and memory available for application execution.
Even relatively low power devices, such as tablets, can display images using only the serial data
stream from output port 114. Examples of high speed serial data modules and other components
that may be included in signal conditioning / processing circuit 110 are discussed in more detail
below with respect to FIGS. As mentioned above, using on-chip analog-to-digital conversion and
high-speed serial data links to offload digital data streams is an "ultrasonic on-chip" solution in
accordance with some embodiments of the present disclosure It is one of the features that helps
to make it easy.
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[0117] [0152] Device 100, such as that shown in FIG. 1, can be used in any of a number of
imaging and / or therapeutic (eg, HIFU) applications and the particular discussed herein. An
example should not be considered limiting. In one illustrative implementation, for example, an
imaging device comprising an array of N × M planes or substantially planes of CMUT elements
may be part of elements in array 102 or one or more transmit phase periods or Energizing all
together (or separately), as well as during one or more receive phase periods, so that the CMUT
element detects the acoustic signal reflected by the object during each receive phase period. By
receiving and processing the signals generated by some or all of the elements therein, the
imaging device itself can be used to obtain an ultrasonic image of an object, for example the
human abdomen. In other implementations, some of the elements in array 102 may be used only
to transmit acoustic signals, and other elements in the same array 102 may be used
simultaneously to receive acoustic signals. be able to. Furthermore, in some implementations, a
single imaging device may include a P × Q array of individual devices, or a P × Q array of
individual N × M planar arrays of CMUT elements. The components can be parallelized to allow
data to be accumulated from a larger number of CMUT elements than can be embodied in a
single device 100 or on a single die 112. It can operate sequentially or according to some other
timing scheme.
[0118] [0153] In yet another implementation, a pair of imaging devices may be arranged to
straddle the object, so that one or more CMUT elements in the imaging device's device 100 on
one side of the object may be targeted The acoustic signal generated by one or more CMUT
elements in the device 100 of the imaging device on the other side of the object can be detected
as long as such a pulse is not significantly attenuated by the object. Further, in some
implementations, the same device 100 is used to scatter acoustic signals from one or more of the
CMUT elements of the device 100 itself, as well as disposed in the imaging device on the
opposite side of the object. Both transmissions of the acoustic signal from one or more of the
CMUT elements can be measured.
[0119] [0154] An illustrative example of an embodiment of an ultrasound unit 200 adapted to
transmit acoustic signals and receive only backscattered pulses from object 202 is shown in FIGS.
2A-2B. The ultrasound unit 200 comprises, for example, one or more devices 100 arranged in an
array on a circuit board (not shown) and supported by the housing of the ultrasound unit 200. In
the exemplary implementation of FIG. 2A, the high speed serial data stream from ultrasound unit
200 may be connected to the serial port (eg, USB port) of computer 204 for further processing
and / or display on computer screen 206. It can be output. As discussed in more detail below,
may a component for achieving such functionality be integrated on one or more dies 112 of the
device 100, or otherwise ultrasound Depending on what is provided in unit 200, if computer 204
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41
is required to perform functions such as waveform removal, imaging, back end processing, etc.
prior to displaying the image on display screen 206 of the computer And may not be required.
[0120] [0155] As shown in FIG. 2B, in another implementation, a high speed serial data stream
from ultrasound unit 200 can be provided to the input port of smartphone 208 for further
processing and / or display. Data processing (e.g., waveform removal, imaging, and / or back end
processing) is possible in some embodiments, as the processing power and memory available for
application execution on this type of device may be limited. Etc.) may be implemented on one or
more dies 112 of the device 100 or otherwise within the ultrasound unit 200. However, in other
embodiments, some or all of such data processing may be additionally or alternatively
implemented by one or more processors on the smartphone 208.
[0121] [0156] Another example of an implementation employing a pair of opposing ultrasound
units 200 is illustrated in FIGS. 3A-3B. As shown in FIG. 3A, a pair of ultrasound units 200 are
arranged to straddle the object 202 (the ultrasound unit 200 behind the object 202 is not visible
in FIG. 3A), a desktop computer or workstation A serial stream of data can be output at 306. FIG.
3B illustrates how the transducer array 102 of the device 100 can be positioned to image an area
302 within the object 202. As discussed above, depending on the imaging techniques and
methodologies employed, individual transducer elements 304 in a given array 102 may be used
to generate an acoustic signal or receive an acoustic signal, or You can do both. Any of the above
examples allow, for example, 2D brightness mode (B mode), 3D B mode, or tomographic
ultrasound imaging.
[0122] [0157] In some embodiments, the devices and architectures disclosed herein can be fully
integrated with one or more advanced methods, such as, for example, one or more synthetic
aperture techniques. Synthetic aperture techniques can allow, for example, the formation of high
resolution images from a collection of multiple receiving apertures. Examples of such techniques
include, but are not limited to: (1) transmit and receive on all pairs of transducer elements, (2)
plane wave synthesis, (3) reverse scattering solution for any transmit mode, ( 4) interpolation
range movement (e.g. Stolt interpolation) or other Fourier resampling techniques, (5) dynamic
focus, (6) delay addition processing, and (7) virtual sources.
[0123] [0158] Many examples of other configurations and implementations of the array of
ultrasonic transducer elements 304 that may be additionally or alternatively employed using
device 100 such as those disclosed herein are referenced above. Co-pending and co-owned US
patent application Ser. No. 13 / 654,337, filed Oct. 17, 2012, entitled "TRANSMISSIVE IMAGING
AND RELATED APPARATUS AND METHODS".
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42
[0124] [0159] FIG. 4A provides an illustration of how individual transducer elements 304 in
transducer array 102 can be arranged with respect to CMOS circuit 402 (including TX control
circuit 104 and / or RX control circuit 106) for that transducer element 304. Here is a helpful
example. As shown, in some embodiments, each transducer element 304 can be associated with
its corresponding TX control circuit 104 and RX control circuit 106. Details of an exemplary
implementation of such a circuit are described below. In the embodiment shown in FIG. 4A, each
of the transducer elements 304 has its corresponding TX control circuit to facilitate, for example,
interconnections, minimizing cross talk between components, minimizing parasitic capacitance,
etc. 104 and / or directly on the RX control circuit 106. (As previously discussed, how the
transducer cell (eg, transducer cell 602 described below), transducer element 304, and
transducer array 102 are integrated with the CMOS circuitry in this manner, Otherwise, details
on whether they are formed on top of the CMOS circuit are incorporated by reference above,
entitled "COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) ULTRASONIC
TRANSDUCTORS AND METHODS FOR FORMING THE SAME" No. 61 / 794,744, filed Mar. 15,
2013, having B.sub.1348.70007 and US.sub.00. )
[0125] [0160] However, in other embodiments, one or more of the transducer elements 304 may
be associated with one or more TX control circuits 104 and / or one or more RX control circuits
to achieve other benefits or advantages. It should be understood that, for 106, other
arrangements can be made. Further, as mentioned above, in some embodiments, some or all of
the components of TX control circuit 104 and / or RX control circuit 106 may be die 112, device
100, and / or ultrasound. It should be understood that the unit 200 can be omitted. In certain
embodiments, for example, the functionality of TX control circuit 104 and / or RX control circuit
106 may be implemented by different chips, or even different devices, eg, computers.
[0126] [0161] FIG. 4B shows an illustrative example of an ultrasound unit 200 comprising
groups of individual ultrasound devices 100a-100d that can operate together under the direction
of the controller 406. The ultrasound devices 100a-100d may be of the type described herein for
the device 100, may be ultrasound on chip devices in some embodiments, or other ultrasound
devices Good. In some embodiments, each of the devices 100a-100d may be a single chip device
including an ultrasound transducer and an integrated circuit.
[0127] [0162] Furthermore, the devices 100a-100d may be identical to one another or may be
different types of devices. For example, in some embodiments, devices 100a-100d can all provide
the same functionality (eg, ultrasound imaging functionality). In some embodiments, one or more
of the devices 100a-100d can be configured as an ultrasound imaging device, and one or more
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can be configured as a HIFU device. In some embodiments, one or more of the devices 100a100d may be controllable to operate as either an imaging device or a HIFU device, or both.
[0128] [0163] Arrangement of 2, 4, 8, 16, or any other amount of any number of individual
devices 100 to form a large area that can be used to emit and / or detect ultrasonic energy It
should be understood that it can be arranged by Thus, the four illustrated devices 100a-100d
represent non-limiting examples. In some such embodiments where multiple devices 100a-100d
are coupled as shown, the devices 100a-100d may be packaged in a common package or
housing, and a common substrate (eg, a plate) Or may be disposed on the interposer) or
mechanically coupled in any suitable manner.
[0129] [0164] An example of a clock generation circuit 1904 that can be included on the die
112 of an individual device 100, in some embodiments, to allow operations of the plurality of
devices 100a-100d to be synchronized is shown in FIG. It is described below with respect to FIG.
[0130] [0165] FIG. 5 illustrates how a single transducer element 304 can fit within the larger
transducer array 102 in some embodiments. 6A-6E illustrate five different examples of how a
given transducer element 304 of circular transducer cells 602 in the array 102 can be
configured in some embodiments. Show. As shown in FIG. 6A, in some embodiments, each
transducer element 304 in the array 102 may include only a single transducer cell 602 (eg, a
single CUT or CMUT). As shown in FIGS. 6B-6E, in other embodiments, each transducer element
304 in the array 102 may include a group of individual transducer cells 602 (eg, CUTs or
CMUTs). Other possible configurations of transducer elements 304 include trapezoidal elements,
triangular elements, hexagonal elements, octagonal elements, and the like. Similarly, each
transducer cell 602 (e.g., a CUT or CMUT) that makes up a given transducer element 304 can
have each transducer cell 602 itself take any of the geometries described above, so that a given
transducer Elements 304 may, for example, be one or more square transducer cells 602,
rectangular transducer cells 602, circular transducer cells 602, star shaped transducer cells 602,
trapezoidal transducer cells 602, triangular transducer cells 602, hexagons Transducer cells 602,
and / or octagonal transducer cells 602, and the like.
[0131] [0166] In some embodiments, at least two (eg, all) of the transducer cells 602 in each
given transducer element 304 serve as a unit and respond to the same pulser output (described
below) Together generate an emitted ultrasonic pulse and / or receive an incident ultrasonic
pulse together to drive the same analog receiving circuit. When multiple transducer cells 602 are
included in each transducer element 304, the individual transducer cells 602 can be arranged in
any of a number of patterns, and for a given application, for example, directivity, signal pairs
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Specific patterns are selected to optimize various performance parameters such as noise ratio
(SNR), field of view, and the like. In some embodiments where a CUT is used as the transducer
cell 602, individual transducer cells 602 can have a film thickness of about 0.5 to 1.0 μm, for
example, with a width on the order of about 20 to 110 μm. The individual transducer elements
304 have a depth on the order of about 0.1 to 2.0 μm, and can have a diameter of about 0.1 mm
to 3 mm, or any value in between. These are merely illustrative examples of possible dimensions,
but larger and smaller dimensions are possible and contemplated.
[0132] [0167] For example, Bavaro, V., which is incorporated by reference in its entirety. らの「
Element Shape Design of 2−D CMUT Arrays for
Reducing Grating Lobes, IEEE Transactions on
Ultrasonics, Ferroelectrics, and Frequency
Control, Vol. 55, No. The geometry of the transducer elements 304 and the
interrelationships between the transducer elements 304 can be selected to optimize the
performance parameters of the transducer array 102, as described in US Pat. Embodiments of
the ultrasonic devices described herein can employ such techniques. 7A-7B illustrate an
illustrative example in which the transducer cells 602 (eg, CUT or CMUT) of the star-shaped
transducer element 304 are mixed, and FIG. 7C achieves advantages such as grating lobe
reduction. An illustrative example is shown in which the transducer cells 602 of the circular
transducer element 306 are mixed.
[0133] [0168] In some embodiments, similar effects such as reducing grating lobes may be used
in addition to mixing transducer elements 304 in array 102, or instead of mixing transducer
elements 304 in array 102. The one or more transducer cells 602 in a given transducer element
304 are accomplished by coupling with one or more transducer cells 602 in one or more
adjacent or nearby transducer elements 304. be able to. By using such techniques, a given
transducer cell 602 need not belong to only a single transducer element 304, but instead can be
shared by multiple transducer elements 304, so that the entire transducer area is Better use can
be realized. This cell sharing technique, in some embodiments, allows a number of transducer
cells 602 in transducer element 304 to emit less power than other transducer cells 602 in the
same element and It can be combined.
[0134]
[0169]
An illustrative example of a suitable cell sharing technique is shown in FIG. In this example,
transducer cells 602 (eg, CUT or CMUT) around transducer element 304 are coupled to one
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another via coupling element 802. In some embodiments, coupling element 802 can comprise,
for example, a polysilicon resistor. In other implementations, coupling element 802 may
additionally or alternatively comprise capacitive and / or inductive elements or features. For
example, inductive coupling can be created between pairs of transducer cells 602 by extending
the conductors for transducer cells 602 to be coupled in close proximity to one another. In some
embodiments, particular transducer cells 602, such as transducer cells 602 around shared
transducer elements 304, can be further operated according to a desired apodization scheme. In
the embodiment shown in FIG. 8, for example, an apodization scheme may be applied to
transducer cells 602 coupled to transducer cells 602 among other elements, such that they are
not so coupled. It emits a smaller output than the transducer cell 602.
[0135]
[0170]
In some embodiments, it is also advantageous that different impedance values be used between
different pairs of transducer cells 602, depending, for example, on the proximity of the
transducer cells 602 to the periphery of the transducer elements 304 of the transducer cells
602. There is a possibility. In some embodiments, for example, a pair of transducer cells 602,
both of which are located around two transducer elements 304, is a pair of transducer cells 602
in which one of the transducer cells 602 is not around that transducer element 304. Can be
coupled together with an impedance value greater than the impedance value used to couple them
together. This possible configuration is illustrated in FIG. As shown, the transducer cells 602a
around the two transducer elements 304 can be coupled together via a junction 802a (eg, a
polysilicon resistor) having a resistance value R1, while the transducer elements 304 are A
transducer cell 602b closer to the center of the can be coupled to another transducer cell 602 via
a coupling 802b having a resistance value R2. Resistance value R2 may be, for example, larger
than resistance value R1. In some embodiments, a gradually increasing impedance value gradient
may be employed from the periphery to the central portion of the transducer element 304.
Again, such cell sharing techniques that employ different impedance values or gradients of
impedance values can be combined with the apodization technique to optimize the performance
of the array 102 for a particular application.
[0136]
[0171] As mentioned above, the above techniques for sharing and / or apodizing transducer
elements 304 in array 102 are either symmetrical or asymmetrical, and uniformly around the
periphery according to some gradient Or otherwise, it can be combined with the mixing
techniques discussed above, so that the transducer element 304 mixes and both around it, or via
gradients of impedance values, or otherwise It can have transducer cells 602 coupled together.
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[0137]
[0172]
FIG. 10 illustrates how, in some embodiments, the transducer element 304 is energized to
ultrasonic pulses using either the TX control circuit 104 and the RX control circuit 106 for a
given transducer element 304. Is a block diagram illustrating whether to emit or to receive and
process a signal from transducer element 304 that represents an ultrasonic pulse detected by
transducer element 304.
In some implementations, TX control circuit 104 may be used for the "transmit" phase period
and RX control circuit may be used for the "receive" phase period that does not overlap with the
transmit phase. In other implementations, one of TX control circuit 104 and RX control circuit
106 may simply be implemented within a given device 100, such as when a pair of ultrasound
units 200 is used for transmissive imaging only. It may not be used. As mentioned above, in some
embodiments, device 100 may alternatively employ only TX control circuit 104 or only RX
control circuit 106, and aspects of the present technology may Does not necessarily require the
presence of various types of circuits. In various embodiments, each TX control circuit 104 and /
or each RX control circuit 106 may be a single transducer cell 602 (eg, a CUT or CMUT), two or
more transducer cells 602 in a single transducer element 304. , A single transducer element 304
comprising a group of transducer cells 602, a group of two or more transducer elements 304 in
array 102, or an overall array 102 of transducer elements 304.
[0138]
[0173]
In the example shown in FIG. 10, there is a separate TX control circuit 104 / RX control circuit
106 combination for each transducer element 304 in the array 102, but each of the timing &
control circuit 108 and the signal conditioning / processing circuit 110. There is only one case.
Thus, in such an implementation, the timing & control circuit 108 can serve to synchronize and
coordinate all operations of the TX control circuit 104 / RX control circuit 106 combination on
the die 112 Processing circuitry 110 may be responsible for handling the input from all of RX
control circuitry 106 (see element 1004 in FIG. 10) on die 112.
[0139]
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[0174]
As shown in FIG. 10, in addition to generating and / or distributing clock signals for driving the
various digital components in the device 100, the timing & control circuit 108 controls the
operation of each TX control circuit 104. Either a "TX enable" signal to enable the operation or
an "RX enable" signal to enable the operation of each RX control circuit 106 can be output. In the
example shown, to prevent the output of TX control circuit 104 from driving RX control circuit
106, switch 1002 in RX control circuit 106 is always open before TX control circuit 104 is
enabled. It may be. The switch 1002 may be closed when the operation of the RX control circuit
106 is enabled so that the RX control circuit 106 can receive and process the signal generated by
the transducer element 304.
[0140]
[0175]
As shown, TX control circuit 104 for each transducer element 304 can include both a waveform
generator 1006 and a pulser 1008. The waveform generator 1006 may, for example, serve to
generate the waveform applied to the pulser 1008 so as to cause the pulser 1008 to output a
drive signal to the transducer element 304 corresponding to the generated waveform.
[0141]
[0176]
In the example shown in FIG. 10, RX control circuit 106 for each transducer element 304
includes an analog processing block 1010, an analog to digital converter (ADC) 1012, and a
digital processing block 1014. The ADC 1012 may comprise, for example, a 10-bit, 20Msps,
40Msps, or 80Msps ADC.
[0142]
[0177]
After being subjected to processing in digital processing block 1014, all outputs of RX control
circuit 106 on die 112 (in this example, the number of outputs equals the number of transducer
elements 304 on the chip) are signal conditioned / processed. It is sent to the multiplexer (MUX)
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1016 in the circuit 110. MUX 1016 multiplexes the digital data from the various RX control
circuits 106 and the output of MUX 1016 may be, for example, of the last processing before data
is output from die 112 via one or more high speed serial output ports 114. To the multiplexed
digital processing block 1018 in the signal conditioning / processing circuit 110. Exemplary
implementations of the various circuit blocks shown in FIG. 10 are further discussed below. As
described in more detail below, various components in analog processing block 1010 and / or
digital processing block 1014 separate waveforms from the received signal, or otherwise through
a high speed serial data link. Alternatively, it can serve to reduce the amount of data that needs
to be output from the die 112. In some embodiments, for example, one or more of the
components in analog processing block 1010 and / or digital processing block 1014 may thus
have improved signal to noise ratio (SNR) and waveforms as improved by RX control circuit 106.
In a manner compatible with the diversity of H.264, it can work to make it possible to receive
transmitted and / or scattered ultrasonic pressure waves. Thus, the inclusion of such elements
can further facilitate and / or extend the "ultrasonic on chip" solution disclosed in some
embodiments.
[0143]
[0178]
Although specific components, which may optionally be included in analog processing block
1010, are described below, digital counterparts to such analog components are additionally or
alternatively included in digital processing block 1014. Please understand that it can be adopted.
The reverse is also true. That is, although specific components that may optionally be included in
digital processing block 1014 are described below, analog counterparts to such digital
components are additionally or alternatively included in analog processing block 1010. It should
be understood that it can be adopted.
[0144]
[0179]
FIG. 11A illustrates an embodiment of device 100 in which digital processing of the received
signal is not performed on die 112. In some implementations, this embodiment except that RX
control circuit 106 may not employ, for example, ADC 1012 or digital processing block 1014,
and may omit on-chip signal conditioning / processing circuit 110. It may be essentially identical
to the embodiment of FIG. 10 in terms of its basic structure and function. However, in the
embodiment of FIG. 11A, one or more additional buffers / drivers (not shown) may be employed
to drive analog signals on output lines 1102a-b of die 112. I want you to understand.
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[0145]
[0180]
FIG. 11B is an ultrasonic device in which some or all of the waveform generator (not shown) and
other digital circuits discussed herein may be located off-chip rather than on the semiconductor
die 112. 1 illustrates an embodiment. Otherwise, in some embodiments, this embodiment can be
identical to the embodiment of FIG. 10 in terms of its basic structure and functionality. In some
embodiments, the pulser 1008 can be additionally or alternatively placed off-chip.
[0146]
[0181]
FIG. 12A shows an example of circuitry that can be included in each TX control circuit 104 in
some embodiments to allow real time delay and amplification control at any transmit position of
the array 102. In the illustrated example, the waveform generator 1006 is a chirp generator that
includes a set of registers 1202a that can be set to control the characteristics of the chirp
supplied to the three level pulser 1008. Specifically, the phase register "θ 0" controls the start
phase of the chirp, the frequency register "f 0" controls the start frequency of the chirp, and the
rate of change of the chirp over time in the chirp rate register "r" Control. The comparators
1204a-b serve to discretize the waveform signal output by the accumulator 1206, so that the
logic values D0, D1 supplied to the three-level pulser 1008 are in the register 1202a of the
output of the accumulator 1206. Of either of "1, 0", "0, 0", or "0, 1", depending on the
comparison with the values V0HIGH and V1HIGH.
[0147]
[0182]
FIG. 12B shows an alternative embodiment of the waveform generator 1006. In the embodiment
of FIG. 12B, rather than using comparators 1204a-b to discretize the simulated sine wave signal
output by accumulator 1206, look-up table 1212a is used to store accumulator 1206. To
determine if the output of the accumulator 1206 is within the range defined by the values of
V0HIGH and V0LOW in the register 1202b, a look-up table 1212b is used to set the output of
the accumulator 1206 at V1HIGH and V1LOW in the register 1202b. Determine if it is within the
range defined by the value.
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[0148]
[0183]
The configuration and operation of a three-level pulser suitable for use as the pulser 1008 of
FIGS. 12A-12B in accordance with some embodiments, and the benefits of employing such a
pulser to drive a CMUT element, are incorporated by reference in their entirety. Ultrasonic
Imaging Front-End Design for CMUT: A 3 by Kailiang, C. of the "IEEE Asian Solid-State Circuits
Conference" in Kobe, Japan, November 12-14, 2012, which is incorporated herein by reference.
Level 30 Vpp Pulse-Shaping Pulser with Improved Efficiency and a Noise-Optimized Receiver.
Therefore, their details shall not be repeated here.
[0149]
[0184]
In the exemplary embodiment shown in FIGS. 12A-12B, TX control circuit 104 comprises three
levels of control over the timing of the output of pulser 1008. The coarsest level of timing control
is provided by shift register 1208 located at the input of waveform generator 1006 (which may
be programmable, for example, via timing & control unit 108 in some embodiments). Provided.
The next finer level of timing control is provided by the setting of the values ".theta. 0" and "f 0"
in the registers 1202a-b. The finest level of timing control is provided by delay lines 1210a-b,
which are, for example, PIN diodes providing delays on the order of about 72 picoseconds to 22
nanoseconds, or any delay value in between. Can be included, but shorter or longer delays are
also possible and contemplated.
[0150]
[0185]
The embodiments of the waveform generator 1006 described so far are wideband or
narrowband, eg Golay code, Hadamard code, Walsh code, cyclic algorithm new (CAN) coding,
azimuth phase coding, and / or other quadrature waveforms. It may allow coded excitation to be
beamformed and / or also enable generation of gated continuous waves (CW) or impulse
generation. Many additional examples of waveform generation techniques and options are
described in co-pending and shared US patent application Ser. No. 13 / 654,337, incorporated by
reference above, and thus, will be described in further detail herein. It shall not be stated.
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[0151]
[0186]
FIG. 13A is employed by timing & control circuit 108 and each TX control circuit 104 to
selectively determine the values for registers 1202a-b used by waveform generator 1006 in the
embodiment of FIGS. 12A-B. Provides an illustrative example of what can be done. As shown,
each TX control circuit 104 can include an element event memory 1304 that stores values for
registers 1202a-b corresponding to each of a plurality of "TX events" numbers, timing and
control circuits 108 may include an event controller 1302 that serves to communicate a suitable
number of TX events to each of the TX control circuits 104 on the die 112. With such an
arrangement, the waveforms supplied to each transducer element 304 in the array 102 can be
varied from pulse to pulse, by suitably programming the event element memory 1304, for
example the azimuth mentioned above Excitation coding such as coding, ordering of complex
events such as focusing / plane wave scanning can be achieved. Although not shown in FIG. 13, it
should be understood that for operation using the waveform generator embodiment of FIG. 12B,
the values of V0LOW and V1LOW can additionally be provided from element event memory
1304 to waveform generator 1006.
[0152]
[0187]
FIG. 14 shows, in some embodiments, an input for event controller 1302 of timing and control
circuit 108 that can be provided to control both transmit and receive events occurring in
ultrasound device 100. Show the output. In the illustrated embodiment, the event controller
comprises the parameters NTXSamples, NRXSamples, NTXEvents, and NRXEvents, and when
enabled via the enable signal "En", in response to the input clock "Clk", TX and RX events.
Generate and output number and TX and RX enable signals.
[0153]
[0188]
FIG. 15A shows an illustrative example of a routine 1500 that can be implemented by event
controller 1302 to generate a preferred set of outputs for controlling transmit and receive
events. The flowchart on the left hand side of FIG. 15A is an abstraction of the exemplary routine
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illustrated by the flowchart on the right hand side of the figure. As shown, when enable signal
"En" is high, the routine performs between executing TX event subroutine 1502 and performing
RX event subroutine 1504 until enable signal "En" goes low. Police in the street. In the exemplary
routine shown, after being enabled, the routine 1500 first initializes TX and RX event numbers to
"0" (step 1506) and then proceeds to TX event subroutines 1502a-c. The TX event subroutine
1502 causes the TX enable signal to be high (step 1502b) for the number of samples specified
by the NTXSamples parameter, until the current number of TX events exceeds the value of the
NTX Events parameter (step 1502a); The number is increased by one (step 1502c). If the current
number of TX events exceeds the value of the NTX Events parameter (step 1502a), the routine
1500 proceeds to the RX events subroutine 1504.
[0154]
[0189]
The RX event subroutine 1504 causes the RX enable signal to be high (step 1504b) for the
number of samples specified by the NRXSamples parameter, until the current number of RX
events exceeds the value of the NRXEvents parameter (step 1504a); The number is increased by
one (step 1504c). If the current number of RX events exceeds the value of the NRXEvents
parameter (step 1504a), the routine 1500 returns to step 1506, where the number of TX and RX
events are again "0" before starting the TX subroutine 1502 again. It is initialized. By using a
routine such as that shown in FIG. 15A, event controller 1302 can interact with TX control circuit
104 in device 100 so that any number of transducer elements 304 can be in one go A pulse can
be emitted and interact with the RX control circuit 106 so that an acquisition window can be
obtained in a specified manner.
[0155]
[0190]
Possible operation modes of the event controller 1302 using the routine 1500 include (1) single
transmission event / single reception event, (2) multiple transmission event / single reception
event, and (3) single transmission event / multiple There are reception events and (4) multiple
transmission events / multiple reception events. In some embodiments, for example, if it is
desirable for the backscattering mode of operation to follow a number of TX events followed by a
number of RX events followed by an RX event corresponding to each TX event. There is.
Additionally, for more complex events (eg, shear wave backscattering events), it may be desirable
to cycle through a certain number of TX events during each iteration of subroutines 1502, 1504,
followed by a single RX event . These are just a few possible event control methods, but other
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sequences of events are possible and contemplated.
[0156]
[0191]
FIG. 13B shows values for one or more of the operating parameters used by waveform generator
1006 in the embodiments of FIGS. 12A-12B (eg, “θ”, “f0”, “r”, “ V0LOW "," V0HIGH ","
V1HIGH ", and / or" V1LOW ") and / or (discussed below with respect to FIGS. 17, 22, 24, 26, 27,
29, and 30) ), For example, to control LNA 1702, VGA 1704, etc., illustrating another example of
components that can be used to selectively determine values for one or more operating
parameters for RX control circuit . Such values may be stored, for example, for each transducer
element 304 in the set of "next state" registers 1312a-b and the corresponding set of "current
state" registers 1314a-b.
[0157]
[0192]
As shown, peripheral control module 1306, for example USB3 so that external microprocessor
1308 can selectively communicate new values to the next status register 1302 associated with
some or all of transducer elements 304 in array 102. .0 peripheral controller can be integrated
onto the semiconductor die 112; In some embodiments, each group of status registers 1312,
1314 can be controlled by a corresponding register control module 1310a-b. As shown, in some
embodiments, the register control modules 1310a-b can be daisy-chained from one register
control module 1310 to the next.
[0158]
[0193]
FIG. 15B shows an example of a routine 1508 that can be followed to selectively configure the
registers 1312, 1314 in some embodiments. As shown, the microprocessor 1308 can receive the
interrupt signal IRQ via, for example, a USB 3.0 link, before each frame. Upon receipt of such an
interrupt, microprocessor 1308 can determine if the current state of register 1314 needs to be
changed for the next event (see step 1510). If the microprocessor 1308 determines that it should
change states, it may push the new complete sequence down the chain (see step 1512) and latch
the new value into the next state register 1312. it can. The new value in the next status register
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1312 can then be latched into the frame boundary current status register 1302 (see step 1514)
for use in the execution of the next event (see steps 1516 and 1518). . The above process can
then be repeated to latch any desired new value into the next status register 1312. By using such
techniques to selectively control the operating parameters of TX control circuit 104 and / or RX
control circuit 106, for example, the required local memory requirements on die 112 can be
reduced, the microprocessor Because 1308 may have fewer resource constraints than sensor
102, it may be possible to have every pulse have a unique definition with any arbitrary
combination.
[0159]
[0194]
FIG. 16 shows an alternative implementation of an ultrasound device 100 in which a single
waveform generator 1006 can be shared by more than one TX control circuit 104. A shared
waveform generator 1006 can be included, for example, in the timing and control circuit 108. As
shown, rather than using timing and control circuitry 108 to selectively enable TX control
circuitry 104 in a desired sequence, the outputs of shared waveform generator 1006 are each
arranged according to the desired timing sequence. A delay element 1602, selected to cause
pulser 1008 to be reached, may be disposed between the shared waveform generator 1006 in
TX control circuit 106 and each pulser 1008. The delay element 1008 may be located, for
example, in the TX control circuit 104, in the timing and control circuit 108, or elsewhere. The
transducer elements 304 of the array 102 can be pulsed according to any desired timing
sequence, as determined by the delays provided by the respective delay elements 1602, using the
illustrated technique.
[0160]
[0195]
FIG. 17 shows an illustrative example of the components that may be included within the analog
processing block 1010 and the digital processing block 1014 of each RX control circuit 106 (see
FIG. 10). In some embodiments, the components of RX control circuit 106 have, for example, an
overall DC to 50 MHz bandwidth, less than 4 dB noise figure, 45 dB aliased harmonic removal,
and 40 dB channel separation. A gain of 50 dB can be realized. Such parameters are listed for
illustrative purposes only and are not intended to be limiting. Other performance parameters are
possible and contemplated.
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[0161]
[0196]
As shown in FIG. 17, the analog processing block 1010 includes, for example, a low-noise
amplifier (LNA) 1702, a variable-gain amplifier (VGA) 1704, and a low pass filter (LPF). 1706 can
be included. In some embodiments, VGA 1704 can be adjusted via time-gain compensation (TGC)
circuit 1902, which is included, for example, in event controller 1302 of timing and control
circuit 108 (FIG. 19). reference). The LPF 1706 enables anti-aliasing of the acquired signal. In
some embodiments, the LPF 1706 can comprise, for example, a second order low pass filter with
a cutoff frequency on the order of 5 MHz. However, other implementations are possible and
contemplated. As mentioned above, the ADC 1012 may comprise, for example, a 10-bit, 20 Msps,
40 Msps, or 80 Msps ADC.
[0162]
[0197]
In the example of FIG. 17, digital control block 1014 of RX control circuit 106 includes digital
quadrature demodulation (DQDM) circuit 1708, averaging circuit 1714 (including accumulator
1710 and averaging memory 1712), and output buffer 1716. including. DQDM circuit 1708 may
be configured, for example, to mix down a digitized version of the received signal from center
frequency to baseband and then low pass filter and decimate the baseband signal. An illustrative
example of a quadrature demodulation circuit that can be employed as DQDM 1708 is shown in
FIG. As shown, DQDM 1708 may include, for example, mixer block 1802, a low pass filter (LPF),
and decimator circuit 1806. The illustrated circuit enables lossless bandwidth reduction by
removing unused frequencies from the received signal, and thus needs to be processed by the
signal conditioning / processing circuit 110 and offloaded from the die 112 Certainly, the
amount of digital data can be significantly reduced. The bandwidth reduction achieved by these
components can help to facilitate and / or improve the performance of the "ultrasonic on chip"
embodiments described herein.
[0163]
[0198]
In some embodiments, it may be desirable to match the center frequency “fc” of mixer block
1802 to the frequency of interest of transducer cells 602 used in array 102. In some
embodiments, examples of additional components that may be included in RX control circuit 106
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in addition to or instead of DQDM 1708 and / or other components illustrated in FIG. 17 are
shown in FIG. It is described below with respect to FIG. The averaging block 1714 in the
illustrated embodiment (including the accumulator 1710 and the averaging memory 1712)
functions to average the window of received data.
[0164]
[0199]
FIG. 19 shows an exemplary implementation of the timing and control circuit 108. As shown, in
some embodiments, timing and control circuitry 108 can include both clock generation circuitry
1904 and event controller 1302. Clock generation circuit 1904 can be used, for example, to
generate some or all of the clocks used throughout device 100. An exemplary implementation of
clock generation circuit 1904 is shown in FIG. As shown, in some embodiments, a high speed (eg,
1.5625 GHz) clock can be generated that can be sent to clock generation circuit 1904 using, for
example, oscillator 2004 and phase locked loop (PLL) 2006. An external circuit 2002 can be
used to In addition to sending to the serializer / deserializer (SerDes) circuit 2008, the clock is at
a first frequency used to clock a particular component on the die 112 ( For example, it can be
stepped down through frequency divider circuit 2010 and further down to a second frequency
(eg, through frequency divider circuit 2016) for use by other components on die 112 can do. In
some embodiments, for example, frequency divider circuit 2010 can divide the 1.5625 GHz clock
to provide a 40 MHz clock on clock line 2022 for use in die 112, the frequency divider Circuitry
2016 may further divide the 40 MHz clock to provide a 20 MHz clock on clock line 2024, for use
in a die.
[0165]
[0200]
As shown, in some embodiments, the die 112 can have terminals 2026, 2028 respectively
connected to the inputs of the multiplexers 2012, 2018 to receive clock signals from an external
source, the clock It is possible to additionally have output terminals 2030, 2032 connected
respectively to the outputs of the multiplexers 2012, 2018 in order to be able to send the signal
off chip. With proper control of the multiplexer, this configuration can allow multiple chips to be
synchronized by daisy-chained clocks. Thus, for some implementations, this technique extends
multiple devices 100 to fully synchronized, coherent M × N arrays of devices 100 that can
operate as a unit for imaging an object. It becomes possible.
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57
[0166]
[0201]
Returning to FIG. 19, an event controller 1302, which is one illustrative example and can be
included in the timing & control circuit 108, is described above with respect to FIG. 13A.
However, as shown in FIG. 19, in some embodiments, the event controller 1302 can, for example,
use a TGC circuit 1902 that can be used to control the gain of the VGA 1704 in the analog
processing block 1010 of the RX control circuit 106, It can be additionally provided.
[0167]
[0202]
FIG. 21 shows an illustrative example of components that can be included in the multiplexed
digital processing block 1018 of the signal conditioning / processing circuit 110 on the die 112.
As shown, the multiplexed digital processing block 1018 can include, for example, a requantizer
2102 and a USB 3.0 module 2104. In some embodiments, the requantizer 2102 may perform
lossy compression, eg, to provide bandwidth reduction. Requantizer 2102 can operate in any of a
number of manners, and aspects of the present technology do not necessarily require the use of
any particular type of requantization technique. In some embodiments, requantizer 2102, for
example, finds the maximum amplitude of the incoming signal, scales all signals until the
maximum signal is full scale, and then lower-orders N bits from the signal. May be thrown away.
In other embodiments, the requantizer 2102 may additionally or alternatively convert the signal
to logarithmic space, keeping only N bits of the signal. In yet another embodiment, the
requantizer 2102 may additionally or alternatively employ Huffman coding and / or vector
quantization techniques.
[0168]
[0203]
As shown in FIG. 21, one option for outputting a high speed serial data stream from die 112 is a
USB 3.0 module. Details on the structure and operation of such USB 3.0 modules can be found,
for example, in http: // www. usb. It is described in "Universal Serial Bus Revision 3.0
Specification" which is available at org. Although FIG. 21 illustrates using a USB 3.0 module to
provide a high speed serial data stream from the chip, it should be understood that other data
output techniques can be added or alternatively. For example, one or more 10 GB, 40 GB, or 100
GB Ethernet modules may be additionally or alternatively employed. Other high speed parallel or
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high speed serial data output modules and / or techniques may be additionally or alternatively
employed in other embodiments.
[0169]
[0204]
FIG. 22 shows an exemplary implementation of RX control circuit 106, including, for example,
matched filter 2202 that can perform waveform removal to improve the signal-to-noise ratio of
the receiving circuit. Although labeled as a "matched" filter, the filter circuit 2202 may actually
operate as either a matched filter or a mismatched filter to separate the waveform from the
received signal. The matched filter 2202 can work with either linear frequency modulation (LFM)
or non-LFM pulses.
[0170]
[0205]
An illustrative embodiment of a circuit suitable for use as matched filter 2202 is shown in FIG. As
shown, matched filter 2202 may include, for example, padding circuit 2302, fast Fourier
transform (FFT) circuit 2304, multiplier 2306, low pass filter 2308, decimator circuit 2310, and
inverse FFT circuit 2312. If employed, padding circuit 2302 may apply padding to the incoming
signal, for example, sufficient to avoid artifacts from the FFT implementation of the circular
convolution.
[0171]
[0206]
To operate as a "matched" filter, the value of "H (ω)" applied to the multiplier 2306 must be a
conjugate of the transmit waveform Tχ (ω). In some embodiments, filter 2202 can thus actually
operate as a "matched" filter by applying a conjugate of the transmit waveform Tχ (ω) to
multiplier 2306. However, in other embodiments, the “matched” filter 2202 may operate as a
“mismatched” filter, which may instead apply to the multiplier 2306 any value other than the
conjugate of the transmit waveform Tχ (ω). Can.
[0172]
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59
[0207]
FIG. 24 shows another exemplary implementation of RX control circuit 106. In the embodiment
of FIG. 24, RX control circuit 106 includes a de-chirp circuit 2402 that can implement yet
another technique for bandwidth reduction by isolating the signal of interest. Dechirping circuits
are sometimes also referred to as "digital ramps" or "stretching" circuits. In various embodiments,
de-chirping circuit 2402 may be included in analog processing block 1010 or may be included in
digital processing block 1014 of RX, or analog processing block 1010 and digital processing
block of RX control circuit 106 It may be included in both 1014. By using a dechirp circuit on the
LFM waveform, we efficiently convert time to frequency.
[0173]
[0208]
An example of a digital dechirp circuit 2302 is shown in FIG. As shown, the dechirping circuit
2402 can include a digital multiplier 2502, a digital low pass filter 2504, and a decimator circuit
2506. (Analog dechirp circuits will be discussed below with respect to FIG. 26 but will employ
analog multipliers and filters rather than digital multipliers and filters and will not include
decimator circuit 2506. 25. The “reference chirp” shown in FIG. 25 may be, for example, the
same “chirp” as that generated by the waveform generator 1006 in the corresponding TX
control circuit 104.
[0174]
[0209]
FIG. 26 shows yet another exemplary implementation of RX control circuit 106. In this example,
instead of using the DQDM circuit and the digital dechirping circuit in the digital processing
block 1014, an analog quadrature demodulation (AQDM) circuit 2602 and an analog dechirping
circuit 2604 are included in the analog processing block 1010. Included in In such an
embodiment, the AQDM 2602 employs, for example, an analog mixer (not shown) and a local
oscillator (not shown) to mix the incoming signal to baseband, which is then unnecessary from
the analog signal. A low pass analog filter (not shown) can be employed to remove the frequency.
As shown in FIG. 26, this implementation of two ADCs 2606a-b (eg, two 10-bit, 10Msps, 20Msps,
or 40Msps ADCs) to convert the output of the analog dechirping circuit 2604 into digital signal
form. Although can be employed in form, each of the ADCs 2606a-b can be implemented at half
the speed of the ADC 1012 employed in other embodiments, thus potentially reducing power
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consumption.
[0175]
[0210]
Yet another example of RX control circuit 106 is shown in FIG. In this example, low pass filter
2702 and multiplexer 2704 are included in digital processing block 1014 along with averaging
block 1714. In some embodiments, low pass filter 2702 may comprise, for example, a half band
decimated finite impulse response (FIR) filter, the operation of which may be configured to
minimize the number of non-zero taps. An illustrative example of such an FIR filter 2702 is
shown in FIG.
[0176]
[0211]
In various embodiments, each RX control circuit 106 can use any of the analog and digital
circuitry described above alone or in combination with any of the other described circuitry, and It
should be understood that the aspects of the technology do not necessarily require the particular
configurations and / or combinations illustrated herein. For example, each RX control circuit 106
may be AQDM 2602, analog dechirping circuit 2604, DQDM 1708, matching and in some
embodiments provided that analog-to-digital and / or digital-to-analog conversion is performed
as needed. And / or include any one or more of mismatched filter 2202, digital dechirping circuit
2402, averaging block 1714, and low pass filter 2702 in any combination and in any order with
respect to the other components. Can. Importantly, practical implementation of the "ultrasonic on
chip" design described herein for some embodiments by using any or all of the above-described
bandwidth reduction techniques It can help to make possible and commercially viable solutions.
[0177]
[0212]
FIG. 29 illustrates an example of a novel technique for biasing the transducer elements 304 in
the array 102. As shown, each side of the transducer element 304 facing the patient can be
connected to ground to minimize the risk of electrical shock. The other side of each transducer
element 304 can be connected to the output of pulser 1008 via a resistor 2902. Thus, each
transducer element 304 is always biased via the output of pulser 1008 regardless of whether
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switch S1 is open or closed. In some embodiments, for example, embodiments employing a
transducer element 304 comprising one or more CUTs or CMUTs, the bias voltage applied to the
element may be on the order of 100V.
[0178]
[0213]
As illustrated in the accompanying timing diagram of FIG. 29, switch S1 may be closed during
transmit operation and may be open during receive operation. Conversely, the switch S2 may be
closed during the reception operation period and may be open during the transmission operation
period. (There is always a gap between the opening of switch S1 and the closing of switch S2, as
well as between the opening of switch S2 and the closing of switch S1, to ensure that pulser
1008 does not apply outgoing pulses to LNA 1702 in RX control circuit 106). It should be noted
that )
[0179]
[0214]
As also shown in the timing diagram, the pulser 1008 sets the bottom plate of the transducer
element 304 at all times except when the pulser 1008 is applying a waveform pulse to the
transducer element 304 of the pulser 1008 and sets the pulser 1008 high. The output level can
be maintained and the waveform pulse applied during the transmit phase can be referenced to
the high output level of the pulser 1008. Thus, each individual pulser 1008 can maintain an ideal
bias for the corresponding transducer element 304 of pulser 1008 at all times. As shown in FIG.
29, capacitor 2904 blocks the DC bias signal (ie, the high output of pulser 1008) from reaching
LNA 1702 during the receive operation period (ie, when switch S2 is closed), It can be disposed
between the switch S2 and the LNA 1702 of the RX control circuit 106.
[0180]
[0215] By biasing the transducer elements 304 through the pulsars 1008 of each of the
transducer elements 304, a number of otherwise reduced crosstalk, for example, which would
occur if the elements 304 were biased through a common bus Benefits can be provided in some
embodiments.
[0181]
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62
[0216]
FIG. 30 shows another illustrative example of a technique for biasing the transducer elements
304 in the array 102.
As in the embodiment of FIG. 29, the side of the transducer element 304 facing the patient can
be grounded and the switch S1 can be placed between the output of the pulser 1008 and the
other side of the transducer element 304 it can. The switch S 2 in this case can be placed directly
between the non-grounded side of the transducer element 304 and the LNA 1702 of the RX
control circuit 106. In this example, a capacitor is not placed between the switch S2 and the LNA
1702, thus resulting in a potentially significant savings of the footprint on the die 112 that
would otherwise be consumed by such capacitor. In some embodiments, one of the two switches,
either switch S1 or switch S2, can always be closed. In transmit mode, switch S1 can be closed
and switch S2 can be open. Conversely, in receive mode, switch S2 can be open and switch S1
can be closed.
[0182]
[0217]
In order to create a suitable bias voltage at the output of each pulser 1008 and at the input of
each LNA 1702, bias the other side of the transducer element 304 (e.g. the top metal layer of the
transducer array 102) as illustrated in FIG. The entire die 112 can be biased at a bias voltage that
is optimal for the transducer element 304 (except for the parts used for Thus, this arrangement
can facilitate safe high voltage biasing of the transducer element 304 through both the pulser
1008 and the LNA 1702 at all times. In some embodiments, the chip's power supply can be
floated, so that the chip's power supply is not grounded and some or all of the control,
configuration, and communication inputs / outputs to the die 112 are For example, it can be
isolated using light isolation techniques or properly sized capacitors, thus DC blocking any high
voltage remaining on the chip.
[0183]
[0218]
FIG. 31 serves to illustrate the components that can be included in the multiplexed digital
processing block 1018 of the signal conditioning / processing circuit 110 on the die 112 in
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addition to or instead of the components discussed above with respect to FIG. An example is
shown. In some embodiments, one or more of the illustrated components, if a sufficiently small
process is used for CMOS or other integrated circuit fabrication methods employed to fabricate
the die 112. Can be integrated on the die 112 with some or all of the other circuits described
herein.
[0184]
[0219]
In the example of FIG. 31, the signal conditioning / processing circuit 110 comprises a
requantizer module 2102, a waveform removal circuit and / or software 3102, an imaging circuit
and / or software 3104, a back end processing circuit and / or software 3106, and The USB 3.0
module 2104 is included. As the requantizer module and the USB 3.0 module, and their
alternatives are discussed above with respect to FIG. 21, their components will not be further
discussed here. As shown, in some embodiments, one or more processors 3108, such as, for
example, a CPU, a GPU, etc., and / or large scale memory are implemented via software routines
executed by such components. Other than the device 100 described above, which allows some or
all of waveform removal functionality, imaging functionality, and / or back end processing
functionality, as described below. It can be integrated on the die 112 along with the other circuits
discussed above to achieve the other functionality of the component. Thus, in such embodiments,
the waveform removal module 3102, the imaging module 3104, and / or the back end
processing module 3106 shown in FIG. 31 may either be on the die 112 or one or more off chip
memory modules. It can be implemented partially or totally via software stored in the memory of
In some embodiments, employing one or more high speed busses 3110 or similar components,
such as those used by a unified northbridge, positioned on die 112 or some off-chip High speed
data exchange can be enabled between the processor 3108, memory modules, and / or other
components that are either arranged in position. In other embodiments, some or all of such
functionality of imaging module 3104 and / or back end processing module 3106 use one or
more dedicated circuits integrated on die 112 Can be implemented additionally or alternatively.
[0185]
[0220]
In some embodiments, the waveform removal circuitry and / or software 3102 may, for example,
perform RX control circuitry 106 to perform waveform deconvolution, dechirping, FFT, FIR
filtering, matched filtering and / or mismatched filtering, etc. Circuits and / or software may be
included similar to those discussed above with respect to. Any or all of the above functionality
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may be performed by the waveform removal circuitry and / or software 3102 on the die 112,
either alone or together with other functionality, in any order. Alternatively, in some
embodiments, such waveform removal circuitry and / or software 3102 is separate from the die
112, but within the ultrasound unit 200 and its circuit board, and / or its housing Can be placed
with the die 112.
[0186]
[0221]
In some embodiments, the imaging circuitry and / or software 3104 may be, for example,
apodization, backprojection and / or fast hierarchy backprojection, interpolation range
movement (eg, Stolt interpolation) or other Fourier resampling techniques, Circuitry and / or
software configured to perform dynamic focus techniques, and / or delay and add techniques,
tomographic reconstruction techniques, etc. may be included. Any or all of the above
functionality may be performed by the imaging circuitry and / or software 3104 on the die 112,
either alone or together with other functionality, in any order. In some embodiments, the imaging
circuitry and / or software 3104 and the waveform removal circuitry and / or software 3102 can
both be located on the die 112. Alternatively, in some embodiments, such imaging circuitry and /
or software 3104 and / or waveform removal circuitry and / or software 3102 are separate from
the die 112 but the ultrasound unit 200 and It can be placed with the die 112 in the circuit
board and / or in the housing.
[0187]
[0222]
In some embodiments, back-end processing circuitry and / or software 3106 on die 112 may be,
for example, down-range and / or cross-range autofocus, frequency dispersion compensation,
non-linear apodization, remapping, compression, noise removal It may include circuitry and / or
software configured to perform, compounding, Doppler, elastography, spectroscopy, and / or
basis tracking techniques, and the like. Any or all of the above functionality may be performed by
back-end processing circuitry and / or software 3106 on die 112, either alone or together with
other functionality, in any order. . In some embodiments, back-end processing circuitry and / or
software 3106, imaging circuitry and / or software 3104, and / or waveform removal circuitry
and / or software 3102 are all located on die 112 Can. Alternatively, in some embodiments, such
back-end processing circuitry and / or software 3106, imaging circuitry and / or software 3104,
and / or waveform removal circuitry and / or software 3102 are provided from die 112.
Although separated, they can be placed with the die 112 in the ultrasound unit 200 and its
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circuit board, and / or in its housing.
[0188]
[0223]
In some embodiments, memory used to achieve some or all of the functionality described above
can be located on-chip, ie, on the die 112. In other embodiments, however, some or all of the
memory used to implement some or all of the described functionality is located off-chip, circuitry,
software, and / or The remainder of the other components can be disposed on the die 112.
[0189]
[0224]
Although not separately shown, in some embodiments, some of the operating parameters of
timing and control circuit 108, individual TX control circuit 104, individual RX control circuit
106, and / or signal processing / control circuit 110. It should be understood that the whole or
all may be selectively configured or programmed via one or more serial or parallel input ports to
the die 112. For example, timing and control circuit 110 includes a set of external writable
registers including values for the parameters NTXSamples, NTXEvents, NRXSamples, and / or
NRXEvents discussed above with respect to FIGS. 14 and 15, and FIGS. The registers 1202 of the
TX control circuit 104 discussed above with respect to 12B can be selectively programmed via
one or more input ports and are described above with respect to FIGS. 17, 18 and 22-28. The
operating parameters of one or more of the components of RX control circuit 106 discussed may
be selectively programmed via one or more input ports, and the re-discipline discussed above
with respect to FIG. Quantizer circuit 2102 and / or USB Operating parameters for one or more
of the .0 circuit 2104 or other modules can be programmed via one or more input ports and / or
the waveforms discussed above with respect to FIG. 31. Operating parameters for one or more of
the removal circuit 3102, the imaging circuit 3104, and / or the back end processing circuit
3106 can be programmed via one or more input ports.
[0190]
[0225]
32A-32B illustrate that some or all of the waveform removal circuitry and / or software 3102,
imaging circuitry and / or software 3104, and / or back end processing circuitry and / or
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software 3106 are off chip, eg, device 100. FIG. 7 illustrates an embodiment that can be located
on separate computing devices 3202, 3206. As shown in FIG. 32A, imaging and back end is
performed by software executed by processor 3204 of computing device 3202 on computing
device 3202 that does not include one or more field programmable gate arrays (FPGAs) 3208.
Waveform removal can be performed along with the processing function. As shown in FIG. 32B,
on or in addition to or in place of processor 3204 of computing device 3206 implementing such
functionality on computing device 3206 including one or more FPGAs 3208, waveforms may be
generated by FPGA 3208 Processing functionality can be implemented.
[0191]
[0226]
As described herein, aspects of the present disclosure allow the integration of ultrasonic
transducer elements and circuitry on a single chip. Ultrasonic transducer elements can be used in
ultrasound imaging applications, HIFU, or both. It should be understood that such elements can
operate at higher voltages than those conventionally used in CMOS integrated circuits, for
example, higher than the voltages typically supported by deep sub-micron CMOS circuits. For
example, such ultrasonic transducer elements operate at voltages between 20V and 120V,
between 30V and 80V, between 40V and 60V, any voltage within their range, or any other
suitable voltage can do. HIFU applications may utilize higher voltages than ultrasound imaging
applications.
[0192]
[0227] Thus, by making such a circuit compatible with higher voltages than conventionally used
in CMOS integrated circuits, ie by operating a standard CMOS deep submicron circuit higher than
conventional voltages. , Can facilitate the integration of ultrasonic transducer elements and
circuits on a single chip.
[0193]
[0228]
There are two main problems that can limit the operating voltage of NMOS and PMOS devices in
CMOS circuits: (1) gate oxide breakdown, and (2) source and drain (diffusion) breakdown.
In many designs, diffusion breakdown is the first limitation, where diffusion is specifically
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designed in field effect transistors (FETs) to breakdown before gate oxide, to protect the gate
oxide. Be done. In order to increase the diffusion breakdown voltage, the relative concentration in
the source / drain region to the substrate should be appropriate. In some embodiments, lower
doping levels in the source and drain regions can increase the breakdown voltage.
[0194]
[0229]
With respect to gate oxide breakdown, an excessive electric field can stress the gate oxide,
resulting in rupture or gate leakage current. In order to increase the gate to drain or gate to
source breakdown voltage, the maximum field must be reduced.
[0195]
[0230]
Various methods can be used to make high voltage CMOS circuits. Such methods can be
implemented, for example, at the level of mask logic operations and device layout. Standard
diffusion junctions in NMOS technology are typically degenerately doped N + to retrograde
doped P-wells on the order of 10 <17> to 10 <18> dopant / cm <3>. It is. 3V devices typically
yield at 6 volts. The source and drain can be defined, for example, by the same implant that
dopes the poly Si gate. This is generally called a self-aligned transistor.
[0196]
[0231]
The standard gate-drain interface is a lightly doped drain (LDD). The LDD can, for example, be
doped to reduce the electric field, but the size can be minimized to keep the device length long
enough to maintain gate control.
[0197]
[0232]
The CMOS circuit can be changed to a high voltage CMOS circuit, for example, by changing the
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diffusion scheme. For example, mask-aligned sources and drains can be employed, using N-well
and P-well regions. For NMOS implementations, the diffusion can be changed to an N-well source
/ drain with a P substrate. For PMOS, the diffusion can be changed to a P-well source / drain
region comprising an N-well and a deep N-well. The sources and drains can be defined by shallow
trench isolation (STI). Alternatively, for higher voltages, the source and drain can be defined by
gap space and thermal diffusion.
[0198]
[0233] Examples of circuit layouts and associated structures that can be used to implement the
high voltage CMOS circuits in the various embodiments described in the present disclosure are
shown in FIGS.
[0199]
[0234]
FIG. 33 shows an example of a high voltage NMOS 3301a and PMOS 3301b layout that can be
used in some embodiments, for example, to provide a high voltage deep sub-micron node.
The reference numbers described in FIG. 33 correspond to the following features and / or
features of the illustrated layout. Large junction breakdown due to 3302-N-well (NW) / P
substrate (Psub 3303), reduced electric field due to 3304-LDD, large junction breakdown due to
3306-P-well (PW) / NW, and Reduced field due to 3308-LDD.
[0200]
[0235]
FIG. 34 shows an example of a very high voltage NMOS 3401a and PMOS 3401b layout that can
be used in some embodiments. The reference numbers described in FIG. 34 correspond to the
following features and / or features of the illustrated layout. Mask-defined doping for 3402-N +
implants, 3404-thermally diffused PW / Psub, 3406-thermally-diffused NW / Psub, mask-defined
doping for 3408-P + implants, 3410- Thermally diffused NW / Psub, and 3412-thermally
diffused PW / Psub.
[0201]
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69
[0236]
FIG. 35 shows an example of a bi-directional or cascode layout of high voltage NMOS 3501 a and
PMOS 3501 b that can be used in some embodiments. The reference numbers described in FIG.
35 correspond to the following features and / or features of the illustrated layout. That is, 3502N-well source and source gate extensions, 3504-N-well drain and gate extensions, 3506-P-well
source and source gate extensions, and 3508-P-well drain and gate extensions.
[0202]
[0237]
FIG. 36 shows an example of a bi-directional or cascode layout of ultra high voltage NMOS
3601a and PMOS 3601b that can be used in some embodiments. The reference numbers
described in FIG. 36 correspond to the following features and / or features of the illustrated
layout. That is, thermally diffused sources and drains in 3602, 3604-Psub, optional P-well gate
implants for increasing 3606-threshold, thermally diffused sources and drains in 3608, 3610Psub, and 3612-Optional N-well gate implant for threshold increase.
[0203]
[0238]
FIG. 37 shows an example of a pulser using high voltage NMOS and PMOS layout with high
voltage switches that can be used in some embodiments. The reference numbers described in
FIG. 37 correspond to the following features and / or features of the illustrated layout. 3702CUT, 3704 and 3706 represent transistor switches. To disable the pulser, set Txp = 0, Txn = 1,
then set Txn = 0 (the PMOS holds state as long as the c-node remains in the low voltage rail).
3708 represents an enable switch for receiving an enable signal rx_en for isolation from high
voltage. The transistor can have a thick channel as illustrated by the thick gate lines in the figure,
which represent high voltage (HV) devices.
[0204]
[0239]
Figures 38A and 38B show examples of dual and quadruple voltage pulse drivers that can be
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70
used in some embodiments, respectively. The reference numbers described in FIGS. 38A and 38B
correspond to the following features and / or features of the illustrated layout. That is, 3802added cascade devices, 3804, terminals of transducer elements driven by 3806-H bridge circuit,
3808-receiving elements. In operation, turn on the switch to receive mode (set Txn = 1, Txp = 0,
then set Txn = 0), 3810-automatically bias on receive, transducer It is a top plate.
[0205]
[0240]
39A-39B show examples of pulsars that do not employ a receive isolation switch that can be
used in some embodiments. The reference numbers described in FIGS. 39A-39B correspond to
the following features and / or features of the illustrated layout. A resistor defined by N-well in
3902-Psub or non-silicided polysilicon on FOX, 3904-high voltage NMOS pull-down device,
direct connection to 3906-RX Less), 3908-auto receive bias, and cascode devices for 3910
double voltage.
[0206]
[0241]
40A and 40B now each show an example of a time-interleaved single-gradient ADC, and its
operation, which can be employed in some embodiments as one or more of the ADC reference
values. . In the illustrated example, N parallel ADCs are used for one channel to take alternating
samples, whereby the sampling frequency of each ADC is much lower than the Nyquist reference.
Such single-gradient ADCs can enable massive sharing of resources such as, for example, bias,
ramp, and gray counters. Such ADC approaches can thus be highly scalable and provide low
power options.
[0207]
[0242]
FIG. 41 shows an example of a time interleaved sample and hold circuit that can be employed in
some embodiments. In the example shown, reference numeral 4102 denotes a step in which even
numbers are sampled and then odd numbers are sampled, and reference number 4104 denotes a
step in which odd numbers are compared and then even numbers are compared. .
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[0208]
[0243]
42A and 42B show an example of a time division high speed ADC and its operation, which can be
employed in some embodiments as one or more of the ADCs referred to herein. Such an ADC can
employ, for example, a pipeline, SAR, or flash architecture. Because a single high speed ADC with
such an architecture can be used to sample N channels, such an ADC approach can significantly
reduce the area requirements.
[0209]
[0244]
The high voltage CMOS circuits described herein can be configured to drive higher voltages than
what can conventionally be achieved with CMOS circuits and to achieve high voltages at deep
sub-micron nodes. In some embodiments, as a non-limiting example, voltages up to about 10 V
can be handled or driven, up to about 20 V can be handled, or driven up to about 30 V Can
handle or drive up to about 40 V, can handle or drive up to about 50 V, can handle or drive up to
about 60 V, any voltage within those ranges, or other Any suitable voltage can be handled or
driven.
[0210]
[0245]
Although several aspects and embodiments of the technology described in this disclosure have
thus been described, it should be understood that various modifications, modifications and
improvements will readily occur to those skilled in the art. Such alterations, modifications, and
improvements are intended to be within the spirit and scope of the technology described herein.
For example, one of ordinary skill in the art may facilitate various other means and / or
structures to perform the function and / or obtain one or more of the results and / or advantages
described herein. As such, each such variation and / or modification is considered within the
scope of the embodiments described herein. One of ordinary skill in the art will be able to
recognize or ascertain, using at most routine experimentation, many equivalents to the specific
embodiments described herein. Accordingly, it is understood that the above-described
embodiments are provided by way of example only and that within the scope of the appended
claims and their equivalents, inventive embodiments may be practiced other than as specifically
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described I want to. In addition, any combination of two or more of the features, systems, articles,
materials, kits, and / or methods described herein may be any feature, system, article, material,
kit, and / or method thereof. Are consistent with one another and are included within the scope
of the present disclosure.
[0211]
[0246]
The above embodiments can be implemented in any of many ways. One or more aspects and
embodiments of the present disclosure, including the performance of the process or method,
implement the process or method, or control the performance of the process or method (eg, a
computer, processor, or other Device) can make use of executable program instructions. In this
regard, one or more programs that, when executed on one or more computers or other
processors, implement a method that implements one or more of the various embodiments
described above. Computer-readable storage medium (or multiple computer-readable storage
medium) encoded by (for example, computer memory, one or more floppy disks, compact disks,
optical disks, magnetic tapes, flash memories, field programmable gate arrays or Various
inventive concepts may be embodied as circuitry in other semiconductor devices, or other
tangible computer storage media. The one or more computer readable media may be portable, so
that one or more programs stored thereon may be loaded onto one or more different computers
or other processors. Various ones of the aspects described in can be implemented. In some
embodiments, computer readable media may be non-transitory media.
[0212]
[0247]
The terms "program" or "software" may be any type of computer code or code that can be
employed to program a computer or other processor to implement the various aspects as
described above. Used herein in a general sense to refer to a set of computer-executable
instructions. In addition, according to one aspect, one or more computer programs, which when
executed perform the methods of the present disclosure do not have to reside on a single
computer or processor; It should be understood that it may be distributed in a modular fashion
between several different computers or processors to implement the aspects.
[0213]
[0248]
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73
Computer-executable instructions may be in many forms, such as program modules, executed by
one or more computers or other devices. Generally, program modules include routines, programs,
objects, components, data structures, etc. that perform particular tasks or implement particular
abstract data types. Typically, the functionality of the program modules may be combined or
distributed as desired in various embodiments.
[0214]
[0249]
Also, data structures may be stored in computer readable media in any suitable form. For ease of
explanation, the data structure can be shown as having fields associated with positions in the
data structure. Such relationships can be similarly realized by allocating storage of fields at
locations in the computer readable medium that convey the relationships between the fields.
However, any suitable mechanism can be used to establish a relationship between the
information in the fields of the data structure, including the use of pointers, tags, or other
mechanisms that establish relationships between data elements.
[0215]
[0250] When implemented in software, whether as provided by a single computer or distributed
among multiple computers, software code may be executed on any suitable processor or
collection of processors.
[0216]
[0251]
Furthermore, it should be understood that the computer may be embodied in any of several
forms, such as a rack mounted computer, desktop computer, laptop computer or tablet computer,
as a non-limiting example.
In addition, the computer is embedded in a device that has suitable processing capabilities that
are not generally regarded as a computer, including personal digital assistants (PDAs), smart
phones, or any other suitable portable or fixed electronic devices. be able to.
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[0217]
[0252]
Also, a computer can have one or more input and output devices. These devices can be used,
inter alia, to present a user interface. Examples of output devices that can be used to provide a
user interface include a printer or display screen for visual presentation of the output, and a
speaker or other audio generation device for auditory presentation of the output. Be Examples of
input devices that can be used as a user interface include keyboards and pointing devices such as
mice, touch pads and digitizing tablets. As another example, a computer can receive input
information in a speech recognition or other audible form.
[0218]
[0253]
Such computers may be interconnected in any suitable form by one or more networks, including
a wide area network such as a local area network or a corporate network, an intelligent network
(IN) or the Internet. Such networks can be based on any suitable technology, can operate
according to any suitable protocol, and can include wireless networks, wired networks, or fiber
optic networks.
[0219]
[0254]
Also, as described, some aspects can be embodied as one or more methods. Implemented as part
of the method can be ordered in any suitable manner. Thus, the embodiments can be constructed
to perform things in a different order than described and, although shown as continuous in the
illustrative embodiments, perform several things simultaneously Can be included.
[0220]
[0255] It is to be understood that all the definitions defined and used herein govern the
definitions in the dictionary, the definitions in the documents incorporated by reference, and / or
the ordinary meaning of the defined terms.
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75
[0221]
[0256] As used herein and in the claims, the indefinite articles "a" and "an" are to be understood
as meaning "at least one" unless explicitly indicated otherwise.
[0222]
[0257]
Here, the phrase "and / or" as used in the specification and in the claims means "either or both"
of the elements to be coordinated, ie, in some cases It should be understood that the elements
exist in conjunction and in other cases the elements exist in disjunction.
Multiple elements listed with "and / or" should be construed as being in the same fashion, ie, "one
or more" of the elements so coordinated.
Other elements may or may not relate to those specifically identified by those other than those
specifically identified by the phrase "and / or", although optional Can exist. Thus, as a nonlimiting example, when used in combination with the open language such as "comprising", the
reference "A and / or B" is only A in one embodiment (optional In other embodiments, only B
(optionally including other than A), and in yet another embodiment both A and B (optionally
including other elements) And so on.
[0223]
[0258]
Here, as used in the specification and claims, the phrase "at least one" in the recitation of one or
more elements is any of the elements in the list of elements. Means at least one element selected
from one or more, but does not necessarily include at least one of every element specifically
listed in the element list, and it is not necessary to It should be understood that any combination
is not excluded. In addition to the elements specifically identified in the list of elements to which
the phrase "at least one" refers, this provision may or may not relate to those elements
specifically identified. Although it is possible, optionally it is also possible that an element can be
present. Thus, as a non-limiting example, “at least one of A and B” (or equivalently, “at least
one of A or B”, or equivalently, “A and / or B At least one of them, in one embodiment,
comprises at least one, optionally two or more, A and B absent (and optionally comprising
elements other than B), another implementation In form there is at least one, optionally including
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two or more, A with A absent (and optionally with elements other than A), and in yet another
embodiment at least one, optionally 2 It can be said that A and at least one, optionally including
two or more, B (and optionally including other elements), and the like.
[0224]
[0259]
Also, the phraseology and terminology used herein is for the purpose of description and should
not be regarded as limiting. As used herein, the terms "including", "comprising", "having",
"containing", "involving" and variations thereof are intended to , Items listed after that, and their
equivalents, as well as additional items, are meant to be included.
[0225]
[0260]
In the claims, as in the above specification, "comprising", "including", "carrying", "having",
"containing", "including" It should be understood that all transition phrases such as (involving),
"holding", "composed of" etc. are open, meaning that they include but are not limited to. Only the
transition phrases "consisting of" and "consisting essentially of" shall be closed or semi-closed,
respectively.
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