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DESCRIPTION JPH02236693

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DESCRIPTION JPH02236693
[0001]
The present invention relates to a digital signal processing apparatus that processes data input in
time series based on a predetermined algorithm and outputs the processed data as time series
data. (A) Prior Art In a simple manner, the primitive information sources that exist around us,
such as voice and images, are often analog signals. A system that processes this analog signal in a
digital manner is a digital signal processor (digital signal processing system: DSP system). In
recent years, the digitalization of digital circuits has rapidly progressed, a DSP system can be
easily realized on one chip, high-precision processing is possible compared to analog signal
processing, and arbitrary characteristics are stabilized by parameter settings. The DSP system
has been rapidly put to practical use because it has features such as being able to be obtained
uniformly and enabling non-adjustment. Further, the application range of the DSP system is
widely used in audio signal processing, communication signal processing, measurement signal
processing, image signal processing, seismic wave signal processing, underwater acoustic signal
processing, and the like. Also, in the audio field, as with CD (compact disc) players and DAT
(digital audio tape) players, DSP systems that digitize audio signals as the digitalization of audio
signals progresses are put to practical use. It has been A conventional DSP system has the
architecture shown in FIG. 6 so that digital filters can be easily formed. In FIG. 6, a data output
bus (I / O) (1), data R A M (2), a multiplier (3), an arithmetic circuit (ALU) (4), an accumulator (
ACC) (5) etc. are connected, the output of data RAM (2) and the output of data ROM (6) are
connected to the multiplier (3), and the multiplication result output of the multiplier (3) is A L U (
It is applied to one input of 4). Each of these circuits is controlled by a microcode signal output
from the decoder (8) that decodes the instruction sequentially read from the program ROM (7) in
response to the instruction. In the implementation of the digital filter, Y = Ax ++ B-x l-1 + c-x l-! A
multiply-accumulate operation of the form ?? appears repeatedly. When this digital filter is
realized by a DSP system, the calculation order of the nodes in the filter is determined, a program
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is created, and the program is stored in the program R O M (7) and the data R O M (6 Store the
calculation formula constant in).
Then, by executing the program, a product-sum operation is performed, and the operation result
is sequentially stored in data R A M (2). (Problems to be solved by the invention) When the DSP
system shown in FIG. 6 is used in the audio field, audio such as graphic equalizer function, bass
treble, loudness, robo-list function and surround effect function However, since audio signals
have two left and right channels, processing for realizing the above functions must be applied to
the left and right channels respectively. Also, in order to change the characteristics of the left and
right channels independently, different constants must be written to the data ROM. Therefore, in
a CD player or DAT player, the sampling period of the signal is a high frequency such as 44.1
KHz or 48 KHz, so all the processing for realizing the above-mentioned function is performed
during the sampling period, the left and right channels. You must finish running on each of the
Therefore, depending on the processing speed of the DSP system, it may not be possible to
realize any of the above mentioned functions. That is, there is a drawback that the throughput of
the DSP system is deteriorated. (2) Means for Solving the Problems The present invention has
been made in view of the above-mentioned point, and has a pair of digital processing circuits for
calculating input digital data according to a predetermined procedure, and A pair of data buses
for transferring data in each digital processing circuit, and a single control for controlling the
pair of digital processing circuits simultaneously or independently with a control signal output by
decoding a preprogrammed instruction By providing the circuit, the signals of the left and right
channels are processed independently and simultaneously, and a digital signal processing device
with improved throughput is provided. According to the above-described means, for example,
when the program for realizing the digital filter is executed, each of the pair of digital processing
circuits is simultaneously controlled by the control signal output from the control circuit, and as
a result, A product-sum operation is simultaneously performed on two input data, that is, data of
the left channel and the right channel, and a filtering operation is performed, so that twice the
throughput can be obtained compared to the prior art. In addition, even when different filter
characteristics are obtained for the left and right channels, the same product-sum operation can
be performed after storing different constants in each digital processing circuit.
(F) Embodiment FIG. 1 is a block diagram showing an embodiment of the present invention, and
is a pair of digital processing circuits (9010) and data buses (BUSI) (Bus 2) of the digital
processing circuits (9) and (10). (11), the interface circuit (13) similarly connected to the data
bus (11), the digital processing circuits (9) (10), the data input / output circuit (12) An audio DSP
system comprising a control circuit (14) for controlling the operation of the interface circuit (13).
The data bus (1 l) is 24 bits each of 8 bits О 3 and 1-11. The data input / output circuit (12)
serializes 16-bit left and right channel sampling data (for example, data with a sampling
frequency of 44.1 KHz in the case of a CD player) externally applied to the input terminal IN.
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Data of the left channel is sent to the BUSI of the data bus (1 l), data of the right channel is sent
to the BUS 2 of the data bus (1 l), and the processed left channel data sent to the data bus BUS1.
And the processed right channel data sent to the data bus BUS2 and alternately output serially
from the output terminal OUT. The interface circuit (13) performs data transmission and
reception between the DSP system and a microcomputer (not shown), and sends out, for example,
the constant of the digital filter applied from the microcomputer to the data bus (11), , System
status data and the like sent to the data bus (11) are sent to the microcomputer. The data
processing circuit (9) is for data processing of the left channel, and the data processing circuit
(10) is for data processing of the right channel, and each has the same configuration. That is, the
data processing circuits (9) and (10) include the data bus (1 l), the data R A M (15), the constant
R A M (16), the constant R O M (17), and the add L / s pointer (18). (19) (20), having a multiplier
(MOL) (21), ALU (22), an accumulator (ACC) (23), and temporary registers (TMP1, TMP2,...) (24)
There is. The data RAM (15) is a first RAM having a capacity of 24 bits} О 128 for storing data
before processing sent out from the data input / output circuit (12) and data after calculation
processing. 11) and connected to the input of the multiplier (21).
The constant R A M (16) is a second RAM having a capacity of 16 bits О 256 for storing a
constant such as a coefficient of the digital filter sent from the interface circuit (13), the data bus
(11) and multiplication Connected to the other input of the switch (21). The address pointer (18)
is composed of 8 bits and designates the address of the data RAM (15) and is controlled and held
by the microcodes INCI and DEC 1 outputted from the control circuit (14). It has a function to
increment (+1) and decrement (-1) address data, incorporates a register that can set an arbitrary
value by program, and a circuit that compares the set value with the address data, and
increments the address data When the result exceeds the set value, it becomes "0", and when the
result of the decrement becomes less than "0", it has a function of becoming the set value, that is,
it has a function of circulating between "0" and the set value. This circular addressing function is
used to simplify the product-sum operation of the digital filter. (Details will be described later.
The address pointer (19) is a 10-bit pointer for specifying the address of the constant R A M (16),
controlled by the microcode INC2 output from the control circuit (14), and increments the
address data It has a function and a function to be cleared to ?0? by the microcode CLEAR 2
output from the control circuit (14). Furthermore, the address pointer (2o) is an 8-bit pointer for
specifying the address of the constant R O M (17), and has a function of decrementing the
address data by the microcode DEC3 output from the control circuit (14). ing. The multiplier (21)
performs multiplication of 24 bits О 16 bits. The A input has 24 pits, the B input has 16 bits, and
the multiplication result is determined one cycle later. Furthermore, multiplication! Input
selection circuits MPXA and MPXB are provided at the eight inputs (21) and B input, and the
input selection circuit MPXA is operated by the microcode A-BUS from the control circuit (14).
The microcode A-DRAM selects the data R A M (15) and applies it to the A input. The input
selection circuit MPXB selects the data bus (11) by the microcode B-Bus, and the microcode B Select constant R A M (16) with CRAM, select constant R O M (17) with microcode B-CROM and
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apply to B input.
The multiplication result is output in 32 bits. A L U (22) is a 32-bit arithmetic circuit, and the
microcode ADD performs addition processing of the 32-bit multiplication result input to one side
and the 32-bit A C C (23) data input to the other side. Of the 32 bits of ACC (23), the upper 24
bits are connected to the data bus (11), and the lower 8 bits are temporary registers by the
auxiliary bus (25). It is continued with the lower 8 bits and 7 bits of (24). The temporary register
(24) is composed of 32-bit registers TMPI, TMP2 to TMP8 and holds up to eight 32-bit data. The
upper 24 bits of each are connected to the data bus (1l) Connected A 32-bit data transfer is
performed between the temporary register (24) and the ACc (23) by the data bus (I1) and the
auxiliary bus (25). The control circuit (14) comprises a program ROM (26) for storing a program,
a program counter (PC) (27) for specifying an address of the program ROM (26), and an
instruction decoder for decoding the read instruction And (+ -DEC) (28). The program ROM (26)
has a capacity of 32 bits x 512, and stores a program for realizing a digital filter and other
necessary programs. The instruction decoder (28) decodes the instruction and outputs a
microcode, and controls the address pointers (18) (19) (20) INCI, INC2, DECI, CLEAR2, DEC3 and
the input selection circuit MPXA , MPXB control. A-BUS. ADD. Controlling A-DRAM, B-BUS, BCRAM, B-CROM, or ALU (22). Output THR etc. Since this microcode is applied to the circuit
common to each part of the data processing circuits (9) and (10), the execution of one instruction
causes the data processing circuits (9) and (10) to simultaneously perform the same control. It
will be. In the DSP system shown in FIG. 1, an example of the instructions required to construct a
digital filter is shown in FIG. In FIG. 2, the MOL instruction is a multiplication instruction, which
selects the target to be input to the input A and the input B of the multiplier (21) and causes the
multiplication to be performed. 18) Increment, decrement or clear of (19) and (20).
The ALU instruction is a control instruction of A L U (22), ALU ADD adds two input data by A L U
(22), holds the addition result in A C C (23), and ALUTHR , It is an instruction to hold the
multiplication result from the multiplier (21) as it is in A cc (23). RAMID. TMPID and TMP2D are
store instructions, and the data of the data bus (11) are stored in the data R A M (15) and the
temporary register (24). ACCS, TMP I S, and TMP 2 S are transfer instructions, and are
instructions for transmitting the data of A C C (23) and temporary register (24) to the data bus (1
l) and the auxiliary bus (25). By the way, in audio signal processing, when realizing a graphic
equalizer, the product represented by V + ? x + A + X + ? + B + x, ?1 c + y + ? + D + y + ? t E
(A, B, C и D и E are constants) It is obtained by cascading a plurality of band digital filters realized
by sum operation. FIG. 3 is to realize a 2-band graphic equalizer by connecting 2-stage direct
connection of 2-stage direct type 11R filter band digital filters. In FIG. 3, (29) Z- 'is a delay
element for unit time (here, sampling period), (30) is a multiplication element of constant A-J,
and (31) is an addition element. X, is input data input to the filter, and z1 is the filter output. In
the case of an audio system, such filtering must be performed on the left channel signal and the
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right channel signal, but in the DSP system shown in FIG. 1, the program implementing the
digital filter of FIG. Since the digital processing circuits (9) and (10) operate in the same way by
one execution of, the filtering process is simultaneously performed on the left channel signal and
the right channel signal. Therefore, in the DSP system shown in FIG. 1, an operation for realizing
the digital filter of FIG. 3 will be described with reference to FIGS. 4 and 5. FIG. 4 is a diagram
showing a program for realizing the digital filter of FIG. 3. FIG. 5 is an allocation diagram of data
stored in data R A M (15) and constant R A M (16). is there. According to the program of FIG. D,
H, G. F. J. In order to carry out in the order of {circle over (3)}, constants are stored in the same
order at the addresses "0" to "9" of the constant R A M (16).
On the other hand, although data of Xis '' InZl is written in every three addresses in data R A M
(15), 1 address is shifted every sampling period, that is, every filtering process period for one
input data X + ++. x1. ???????? By writing + * +, delay data by the delay element (29) is
created. Therefore, in the case of the digital filter shown in FIG. 3, the address pointer (18) has
cyclic address designation of "0" to "7" and the address pointer (19) has rQJ to "9". It is set by the
program so that it becomes cyclic address specification. Here, at the time of executing step rQJ of
the program of FIG. 4 with respect to the input data X, the contents of the data RAM (15) are as
shown in (a) of FIG. ) When (19) both have the address ?0?, multiplication is performed when
step ?0? is executed! Inputs A and B of (21) are data X + ?t (input data two samples before)
stored at address ?0? of data R A M (15) and address of constant R A M (16) Although the
coefficient C stored in "0" is applied, the multiplication result is determined and output in the
next step. At the end of step "0", the instructions API INC and AP2 INC increment both the
address pointers (18) and (19), and the contents become "l". When step rlJ is executed, data R A
M (15) and constant RAM (16) are multiplied in the same manner as step ?O?! The DEX XI-1
and the constant B which are selected as the input of (21) and stored at the address "1" are
applied to the multiplier (21). In addition, the result multiplied by the previous step ?0? passes
the A L U (22) by the instruction ALUTHR, and the first multiplication result C e x I?1 is stored
in A C C (23) . At the end of step "1", the instructions API INC and AP2 INC increment the address
pointers (18) and (19), and their contents become the address "2". Next, when step "2" is
executed, the instruction MULA BUS. The B CRAM selects the data bus (11) for the input A of the
multiplier (2l) and the constant R A M (16) for the input B. On the other hand, the content of
temporary register TMP 1 is sent to the data bus (11) by the instruction TMP I S, and the data
sent to the data bus (11) by the instruction RAM ID is the data designated by the address pointer
(18). It is stored at the address r2j of R A M (15).
At this time, input data Xl externally applied to the data input circuit (12) at each sampling cycle
is stored in the temporary register TMP1 in advance. Therefore, the input data Xi is multiplied! It
is multiplied by the constant A read from the constant R A M (16) by (21), and is stored in the
address ?2? of the data R A M (15). On the other hand, by the instruction ALUADD, the
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multiplication result B o x. Of C * x stored in AC C (23) and the step "l". An addition of-, is
performed, so that Bx + -r + C-xl- * is stored in ACc (23). At the end of the step "2", the address
pointers (18) (19) are incremented, and the contents become the address "3". When step "3" is
executed, data A AM (15) and data y stored in address "3" of the constant RAM (16) are input to
the inputs A and B of the multiplier (2l). And constant E are applied, and the instruction ALUADD
adds the multiplication result A?x of step ?2? and the content B * X + ? ++ C e X + ? * of AC
C (23) in the ALU (22). The addition result A-xl + B-xl-, + C-X1- * is stored in ACc (23). At the end
of step "3", the address pointers (18) and (19) are incremented to become the address "4". When
step "4" is executed, data A AM (15) and data stored in address "4" of constant RAM (16) are
input to the inputs A and B of the multiplier (2l) '+ The constant A is applied, and the instruction
ALUADD causes the multiplication result E ? ? y + ?t of the step ?3? and the contents A?X
1 + B ? ? of the AC C (23) X 1 ? ++ C?X + ? * to be A L The addition result A = x, + B-X +-++
C 'X +-* + E "Y 1-s is stored in A C C (23). At the end of the step "4", the instruction APIDEC, AP2
INC decrements the address pointer (18) to an address "3", and the address pointer (19) is
incremented to an address "5". When step "5" is executed, the data stored at the address "3" of
the data R A M (15) is input to the inputs A and B of the multiplier (21) / l- * and the constant
RAM (16). The constant H stored in the address "5" of.
That is, the multiplier (21) performs the second stage multiplication of the digital filter shown in
FIG. 3 from this step "5". On the other hand, according to the instruction ALUADD, the contents
A?x 1 + B?X + ? ++ C ? ? X 1?s + E?yl? of the calculation results D?Y + ? + and AC C
(23) of step ?4? are A L U The addition result is added in (22), and the addition result A-x ++ B
* Xl-++ C "XI-1 + D" Y +-, + E'3 / +-t is stored in A CC (23). The content of A C C (23) at this time is
the output y, of the first stage digital filter. At the end of step "5", the address pointer (18) is
incremented to be the address "4", and the address pointer (19) is incremented to be the address
"6". When step "6" is executed, data Y +-+ and constant RAM (16) stored in address "4" of data R
A M (15) are input to the inputs A and B of the multiplier (21). The constant G stored in the
address "6" of is applied. Also, instruction ACCS sends out data y1 stored in ACc (23) to data bus
(11), and instruction TMP 2D stores data y1 sent out on data bus (1 l) in temporary register
TMP2 Be done. On the other hand, according to the instruction ALUTHR, the multiplication result
H * y +-* of the step "5" is stored in A C C (23), bypassing A L U (22). At the end of step r6 ", the
address pointers (18) and (19) are incremented to become the address" 5 "and the address" 7 ".
When the step "7" is executed, the data sent to the data bus (11) and the constant R A M (16) are
input to the inputs A and B of the multiplier (21) by the instruction MULA-BUS, B-CRAM. The
constant F stored in the address "7" of. The data yI stored in the temporary register TMP2 is sent
to the data bus (11) and applied to the input A of the multiplier (21) by the instruction TMP2S
and RAMID, and specified by the address pointer (18). The stored data R A M (15) is stored at the
address ?5?. On the other hand, the instruction ALUADD adds the multiplication result coy of
the step "6" coy,-, and A c C (23) H и y + -t in A L U (22), resulting in G-y I-1 + H " y +-* is stored in
A C C (23).
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At the end of step "7", the address pointers (18) (19) are incremented to become address "6" and
address "8". When step "8" is executed, the data A, B and the constant RAM (16) stored in the
address "6" of the data R A M (15) are input to the inputs A and B of the multiplier (2 l). The
constant J stored in the address ?8? of the second address is applied, while the multiplication
result F?y of the multiplication result of the step ?7? and the data G? stored in the A C C (23)
at A L U (22) Y + ?, + H?Y + ? s are added, and as a result, F?y ++ G?y + ? ++ H?y + one s
is stored in A C C (23). At the end of the step "8", the address pointers (18) and (19) are
incremented to become an address "7" and an address "9". When step "9" is executed,
multiplication! To the inputs A and B of (21), the data z1-1 stored at the address "7" of the data
RAM (15) and the constant I stored at the address "9" of the constant RAM (16) are applied. On
the other hand, in A L U (22), the data F ? Y ++ G?Y + ? ++ H ? ? / l? stored in the
multiplication result J ? ? Z l?1 of step ?8? and A C C (23) * Is added, and the addition
result F-yl + G??f, ?, + H и yt?m + J ? ? Z + ?t is stored in A C C (22). When the address
pointers (18) and (19) are incremented at the end of the step "9", the address pointers (18) and
(19) both become the address "0". When step "10" is executed, no multiplication is performed,
and data F-y, + G-y,-+ "stored in the multiplication results I 'Z +-+ and AC C (23) of step" 9 " H ?
? Y 1 ? s + J ? ? Z + ? * is added at A L U (22) + at this time, and the addition result F?) ?
++ G?Y + ? ++ H и ?! + -T + I-2 +-++ J JZ I-1 is stored in A C C (23). The data of ACc (23) at this
time is the output z1 of the second stage digital filter. Finally, when step 1 ?11? is executed,
the data z1 stored in A C C (23) is sent to the data bus (11) by the instruction ACCS, and it is sent
to the data bus (11) by the instruction RAMID. The sent data 2 is stored in the address "0" of the
data RAM (15) designated by the address pointer (18).
At the end of the step "11", the address pointer (18) is incremented to the address "1". Therefore,
when the program is executed again from step y "0", the data R A M (15) addressed by the
address pointer (18) is to be accessed from the address "1". , One address ahead of the previous
start address. By executing the program of the above steps rQJ to "1l", the filtering process is
performed on the input data X, and the content of the data R A M (15) changes as shown in FIG.
5 (port), and the filter output 2, is obtained. In addition, the data X, by advancing the start
address to the next address with respect to the filter processing of the next sampling data X, +.
Delay data for 1 is obtained. Therefore, by repeating and executing the program of steps ?0? to
rl IJ on the sampling data, the data RAM (15) changes as shown in FIG. 5 (иии) (2), and the filter
output 2 1419 2 141... Further, since the above operation is simultaneously performed in the
digital processing circuits (9) and (10), filter output data of the left channel and the right channel
can be obtained simultaneously. Furthermore, before executing the program of FIG. 4, the filter
characteristics of the left channel and the right channel are changed by changing in advance the
constants stored in the constant RAM (16) of the digital processing circuits (9) and (10). That is,
the levels of the graphic equalizer can be left and right independent. In this case, constant writing
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to the constant R A M (16) is performed by transferring the constant applied from the
microcomputer to the interface circuit (13) to the constant R A M (16). As described above,
according to the present invention, by executing the program for realizing the digital filter, one
set of digital processing circuits can be operated at the same time, and one set of digital filters
can be realized. Digital signal processing of the audio signal of the right channel and the right
channel can be performed with about half of the conventional program length, and has an
advantage of increasing the functions that can be realized during the sampling period. Thus, an
easy-to-use DSP device with improved throughput is obtained.
[0002]
Brief description of the drawings
[0003]
FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block
diagram shown in FIG. 1 showing instructions necessary for realizing a digital filter, and FIG. FIG.
4 shows a program for realizing the digital filter of FIG. 3 in the embodiment of FIG. 1, and FIG. 5
shows a data RAM and a constant!
FIG. 6 is a block diagram showing an example of prompting. (9) (10) ... digital processing circuit,
(12) ... data input / output circuit, (13) ... interface circuit, (14) ... control circuit, (11) ... data bus ,
(15) ... data RAM, (16) ... constant RAM, (17) ... constant ROM, (1B) (19) (20) ... address pointer,
(2l) ... multiplication (22) ... ALU, (23) ... accumulator (ACC), (24) ... temporary register, (25) ...
auxiliary bus, (26) ... program ROM, (27 ) ... Program counter, (28) ... Instruction decoder, (29) ...
Delay element. (30) ... multiplication element, (31) ... addition element. Figure 2
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