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DESCRIPTION JPH03131124

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DESCRIPTION JPH03131124
[0001]
[Outline] When a digital PCM audio data signal is processed by the signal processing unit and
then converted to a PWM audio data signal by the PCM-PWM conversion unit and input to the
power amplifier, timing signals such as data shift crossover signal and built-in When it is
detected that the circuit clock signal for operating the signal processing unit and the PCM-PWM
conversion unit in synchronization with the system clock pulse from the quartz oscillator is
detected, the system clock pulse is An audio reproduction circuit in which an auxiliary clock
signal generated by frequency division or the like is supplied from the signal switching unit to
the signal processing unit and the PCM-PWM conversion unit, the signal processing unit by
stopping the data shift clock signal etc. Operation of the PCM-PWM converter etc. Amplifier and
unnecessary direct current to the speaker becomes possible to prevent the flows. BACKGROUND
OF THE INVENTION 1. Field of the Invention The present invention relates to an audio
reproduction circuit for converting a digital PCM audio data signal into a digital PWM audio data
signal and inputting it to a power amplifier. More specifically, the present invention refers to a
digital audio reproduction circuit capable of reproducing the above-mentioned digital audio data
signal as audio without purposely converting it into an analog audio data signal by a D / A
converter or the like. It is a thing. BACKGROUND OF THE INVENTION FIG. 6 is a block diagram
showing a conventional audio reproduction circuit. Here, the main part of the audio reproduction
circuit has a DSP (digital signal processor) or the like consisting of various digital filters, and
reduces quantization noise of the PCM audio data signal DI and performs processing such as
band compression. It comprises a signal processing unit 1 to be performed, and a PCM-PWM
conversion unit 2 for converting the PCM audio data signal DI processed by the signal processing
unit 1 into PWM audio data signals DO and XDO. Furthermore, the above-mentioned audio
reproduction circuit has an input register and an internal memory for temporarily storing various
data calculated by the DSP in the signal processing unit 1 and the PCM-PWM conversion unit 2. .
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The details of the signal processing unit 1 will be described in the section of the embodiment.
FIG. 7 is a timing chart for explaining the operation of FIG. In the signal processing unit 1, in
addition to the PCM audio data signal DI for displaying the level of the analog audio data signal
by a pulse code at a constant sampling cycle Ts, a sampling signal S Y N indicating the sampling
cycle Ts or A data shift clock signal SCK for shifting data for each bit of the pulse code is serially
input as a timing signal ((A), (B) and (C) in FIG. 7).
In this case, the last 16 clocks of the data shift clock signal SCK, that is, a 16-bit pulse code is
used as valid data. Further, one of L channel and R channel (abbreviated as Lch and Rch in FIG. 7)
is selected by channel selection signal LR5EL, and data shift clock signal SCK is selected by clock
selection signal CLKSIEL. Either the rising output data or the falling output data is selected.
Furthermore, the PCM audio data signal DI having the above 16-bit pulse code is a pulse of a bit
after the sampling frequency fs (fs = 1 / Ts) is increased to m times by the signal processing unit
1 for the purpose of improving the SN ratio. The code is band-compressed and input to the PCMPWM converter 2. The PCM-PWM conversion unit 2 converts the above-mentioned bit code to be
displayed at each sampling period Ts / m into corresponding pulse widths and outputs two PWM
audio data signals Do and XDO. ((D) and (E) in FIG. 7). In this case, the output waveform of XDO
is a waveform obtained by inverting Do. Furthermore, these PWM audio data signals DO and
XDO are directly amplified by the digital power amplifier 8 without being converted back to
analog audio signals, and reproduced as voice by the digital speaker 9. Furthermore, in the
above-described digital audio reproduction circuit, a circuit clock signal Sc having a constant
repetition frequency is supplied to operate the DSP and the like of the signal processing unit 1
and the PCM-PWM conversion unit 2 normally. A circuit clock signal generator 6 is provided.
The circuit clock signal generation unit 6 is constituted by a latch circuit or the like which uses as
a system clock pulse sp a high-speed output signal from the built-in crystal oscillator 7 which is a
large tree of the audio reproduction circuit system. The circuit clock signal Sc equal to the
frequency of the data shift clock signal SCK is generated by latching any one of the cross signal
SCK, for example, the data shift clock signal SCK by the system clock pulse Sp. If the signal
processing unit 1 and the PCM-PWM conversion unit 2 are operated in synchronization with the
circuit clock signal Sc, that is, in synchronization with the data shift clock signal SCK and the
system clock pulse Sp, the PCM audio data signal DI is erroneous Can be played without.
[Problem to be Solved by the Invention] As described above, conventionally, the data shift clock
can be processed so that the PCM audio data signal DI can be correctly processed by the signal
processing unit 1 and the PCM-PWM conversion unit 2 of the digital audio reproduction circuit.
The common circuit clock signal Sc is generated based on the signal SCK or the like and supplied
to the signal processing unit 1 and the PCM-PWM conversion unit 2. However, when the data
shift clock signal SCK or the like is stopped due to partial disconnection or the like of the signal
line, the circuit clock signal Sc is also in the stopped state, that is, in the disconnected state, the
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signal processing unit 1 and PCM -PW? 1 The operation of the conversion unit is also stopped.
For this reason, the function of correctly processing the PCM audio data signal DI in the signal
processing unit 1 and the PCM-PWM conversion unit 2 is lost, and a constant DC level current is
used instead of the PWM audio data signals DO and XDO having a plurality of pulses. Is output
and flows into the speaker 9 through the power amplifier 8. As a result, there arises a problem
that the transistor of the power amplifier 8 and the speaker 9 are destroyed. The present
invention has been made in view of the above problems, and the operation of the signal
processing unit and the PCM-PWM conversion unit is stopped when the data shift clock signal
etc. is stopped, and unnecessary direct current flows into the power amplifier and the speaker. It
is an object of the present invention to provide an audio reproduction circuit capable of
preventing the [Means for Solving the Problems] FIG. 1 is a block diagram showing the principle
of the present invention. However, here, only one PWM audio data signal DO is representatively
shown as a signal output from the PCM-PWM conversion unit 2. In addition, about the thing
similar to the component mentioned above, the same reference number is attached | subjected
and represented. In FIG. 1, an auxiliary clock signal generator 3 is provided which generates an
auxiliary clock signal Sa from the system clock pulse Sp from the crystal oscillator 7.
Furthermore, a signal switching unit 4 is provided on the output side of the auxiliary clock signal
generation unit 3 and the circuit clock signal generation unit 6. The signal switching unit 4 is for
selecting the auxiliary clock signal Sa or the circuit clock signal Sc and supplying it to the signal
processing unit 1 and the PCM-PWM conversion unit 2. Furthermore, the circuit clock signal
disconnection detection unit 5 is provided between the circuit clock signal generation unit 6 and
the signal switching unit 4. The circuit clock signal loss detection unit 5 detects a loss of the
circuit clock signal Sc.
[Operation] In the audio reproducing circuit of the present invention, the circuit clock signal
disconnection detector 4 detects the circuit clock signal Sc as soon as the data shift clock signal
SCK or the like is stopped and the circuit clock signal Sc is disconnected. A disconnection is
detected and a detection signal Sd is output. When the detection signal Sd is output, the signal
switching unit 4 which has previously selected the circuit clock signal Sc outputs the auxiliary
clock signal Sa different from the circuit clock signal Sc, and the signal processing unit 1 and The
signal is supplied to the PCM-PWM converter 2. Therefore, even if the data shift clock signal SCK
or the like is stopped, the operation of the signal processing unit 1 and the PCM-PWM
conversion unit 2 can be continued by the auxiliary clock signal Sa, so the output of the PCMPWM conversion unit 2 The level is no longer fixed at a constant DC level. Thus, according to the
present invention, it is possible to prevent unnecessary DC current from flowing into the power
amplifier and the speaker and destroying them by stopping the data shift signal or the like. FIG. 2
is a circuit diagram showing an embodiment of the present invention. However, in this case, the
signal processing unit 1 will be described in detail before the auxiliary clock signal generation
unit 3 (FIG. 2), the signal switching unit 4 and the circuit clock signal disconnection detection
unit 5 are described. Here, the signal processing unit 1 converts the serial signal into a parallel
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signal, the input shift register 11, the m-times oversampling filter 12 that raises the sampling
frequency fs of the PCM audio data signal DI by m, and the PCM It comprises an n-order ?-?
modulation unit 13 which compresses a band of the audio data signal DI and adjusts it so that it
can be processed by the PCM-PWM conversion unit 2. Furthermore, the m-times oversampling
filter 12, the n-order ?-? modulation unit 13 and the PCM-PWM conversion unit 2 have a DSP
composed of various digital filters, and this DSP has a large number of input registers. And
internal memory etc. are attached. However, here, only the l-th RAM 14, the second RAM 24, the
l-th ROM 15, the second ROM 25 and the ixj-bit multiplier 16 included in the m-fold oversampling filter 12 and the n-order ?-? modulation unit 13 are representatively shown. Do. In
the signal processing unit 1, first, three types of PCM audio data signal DI, sampling signal SYN
and data shift clock signal SCK are input to the input shift register 11 in serial form.
Next, serial-to-parallel conversion is performed on the three types of signals by the input shift
register 11 so that only the 16-bit PCM audio data signal DI can be separated from the other
signals. Furthermore, the sampling frequency fs of the PCM audio data signal DI is increased by
the m-times oversampling filter 12 to shift the quantization noise to a high frequency region as
much as possible, thereby improving the SN ratio. This processing can all be performed by the
DSP in real time. Furthermore, if the 16-bit PCM audio data signal DI output from the m-times
oversampling filter 12 is input to the n-order ?-? modulation section 13, PCM audio data of
bits can be obtained without lowering the data accuracy. The signal DI is obtained. Therefore, the
PWM audio data signals DO and XDO can be generated within the dynamic range of the PCMPWM converter 2. Next, configurations of the auxiliary clock signal generation unit 3, the signal
switching unit 4, and the circuit clock signal disconnection detection unit 5 and their operations
will be described. Here, a frequency divider 30 such as a counter that divides the system clock
pulse sp from the crystal oscillator 7 is provided as the auxiliary clock signal generation unit 3.
Furthermore, the signal switching unit 4 is configured of a gate circuit or the like that outputs
either the circuit clock signal Sc or the auxiliary clock signal Sa using the detection signal Sd
from the circuit clock signal disconnection detection unit 5 as a switching control signal.
Furthermore, the circuit clock signal detection unit 5 is composed of at least one or more
detection counters 50 and a digital differentiation circuit 51 for generating a clear signal of
differential form for clearing the detection counters 50. Here, CK of the detection counter 50. CL,
Q and EN respectively indicate a system clock pulse input terminal, a clear signal input terminal,
a counter signal output terminal and an enable signal input terminal. The high-speed output
signal from the crystal oscillator 6 is input as a system clock pulse Sp to the system clock pulse
input terminal CK. Further, the clear signal is inputted to the clear signal input terminal CL from
the digital differentiation circuit 51 at a constant interval. Further, the circuit clock signal Sc is
generated by latching the data shift clock signal SCK with the system clock pulse Sp in a latch
circuit or the like of the circuit clock signal generation unit 6.
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Therefore, the repetition frequency of the circuit clock signal Sc matches the frequency of the
data shift clock signal SCK, that is, the frequency 32 times the sampling frequency fs. FIG. 3 is a
circuit diagram showing a specific example of this embodiment. However, here, only the
frequency divider 30, the signal switching unit 4 and the circuit clock signal disconnection
detection unit 5 in the audio reproduction circuit are shown. In FIG. 3, the frequency divider 30
is configured by forming two 4-bit frequency division counters 31.degree. 32 in two stages.
These two frequency division counters 31 and 32 divide the system clock pulse Sp, and the
auxiliary signal having a frequency close to the repetition frequency of the circuit clock signal Sc
from the counter signal output terminal Q of the second stage frequency division counter 32 The
clock signal Sa is output. Furthermore, the signal switching unit 4 receives the first OR element
40 receiving the circuit clock signal Sc and the detection signal Sd, and the auxiliary clock signal
Sa and the inversion detection signal S'T (a signal obtained by inverting the level of the detection
signal Sd). And a NAND element 42 connected to the output side of the first and second OR
elements 40 and 41, and an inverter 43 for waveform shaping. Furthermore, using the two 4-bit
detection counters 50 and 50 'as the detection counters of the circuit clock signal disconnection
detection unit 5, the carry output terminal CO of the first stage detection counter 50 is detected
at the second stage. It is connected to the carry input terminal CI of the counter 50. The
detection signal Sd is output from the counter signal output terminal Q of the second stage
detection counter 50. Furthermore, in order to make the operations of the two counters 50, 50
'more reliable, the counter output terminal Q is connected to the enable signal input terminal EN
of the counters 50, 50' via an inverter. . Therefore, the enable signal input to the enable signal
input terminal EN can also be used as the inverted detection signal. Further, the digital
differentiating circuit 51 is composed of two latch circuits 52, 53 and one NAND element 54, and
a clear signal is outputted from this NANO element 54. FIG. 4 is a timing chart for explaining the
operation of FIG. First, when the data shift clock signal SCK is input to the signal processing unit
1 (FIG. 2) together with the PCM audio data signal DI, the circuit clock signal Sc having the same
frequency as the data shift clock signal SCK is a circuit clock. The signal is output from the signal
generator 6 (FIG. 2) ((A) in FIG. 4).
On the other hand, in the crystal oscillator 7 (FIG. 2), a high-speed system clock pulse Sp having a
frequency several hundreds times that of the circuit clock signal Sc is constantly output, and this
system clock pulse sp is a detection counter. 50 and 50 'and the system clock pulse input
terminal CK of the latch circuits 52 and 53 are always applied ((B) in FIG. 4). Next, when the
circuit clock signal Sc is input to the terminal of one latch circuit 52, the circuit clock signal Sc is
output from the terminal Q 'of the latch circuit 52 with a delay of one clock of the system clock
pulse. . Further, when the signal from the terminal Q 'is manually input to the terminal of the
other latch circuit 53, an inverted signal obtained by inverting the level of the input signal is
output from the page 7 of the latch circuit 43 by the input signal. It is output delayed by the
delay time. Furthermore, when the input signal and the inverted signal are input to NAND
element 54, a signal having a pulse width equivalent to one clock of the system clock pulse at the
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rise of circuit clock signal Sc, ie, a clear signal obtained by differentiating circuit clock signal Sc. A
signal is output ((C) in FIG. 4). If it is operated while clearing the counters 50 and 50 'by this
clear signal, the number of times of the bamboo system clock pulse Sp may be counted a fixed
number of times (for example, 200 times) as long as the circuit clock signal Sc is output. it can.
Here, when the data shift clock signal SCK, which is a type of timing signal, is stopped due to
partial disconnection of the signal line or the like, the circuit clock signal Sc is cut off and no
pulse is generated ((A in FIG. )). For this reason, the digital differentiation circuit 5 is in a state
where the rear signal is not output, and the detection counter 50, 50 'counts the number of
pulses more than 200 times. If the maximum count number of the counters 50 and 50 'is set to
250 in advance, the level of the counter signal output terminal Q of the detection counter 50' is
"L" when the 250 counts are completed. Low, changing from ?H? to ?H? (High) to output
?H? detection signal Sd indicating disconnection of the circuit clock signal Sc ((D) in FIG. 4). At
the same time, the inverted detection signal is taken out from the enable signal input terminal EN
of the detection counters 50 and 50 '. On the other hand, the auxiliary clock signal Sa is
constantly output from the counter signal output terminal Q of the second stage frequency
division counter 32 ((E) in FIG. 4).
Furthermore, the circuit clock signal Sc and the detection signal Sd are ORed with the first OR
element 40 of the signal switching unit 4 and the second OR element 41 is ORed with the
auxiliary clock signal Sa and the inverted detection signal. When these OR operation results are
later input to the NAND element 42, a signal as shown in FIG. 4F is output from the inverter 43.
Here, when the data shift clock signal SCK is input to the signal processing unit 1, the circuit
clock signal Sc is output from the inverter 43, and when the data shift clock signal SCK is
stopped, the auxiliary clock signal is output. Sa is output. Therefore, even if the circuit clock
signal Sc is cut off due to the stop of the data shift clock signal SCK, the auxiliary clock signal Sa
is immediately replaced by the signal processing unit 1 and the PCM-PWM conversion unit 2 2),
it is possible to continue the operation of the signal processing unit 1 and the PCM-PWM
conversion unit 2. As a result, the output level of the PCM-PWM conversion unit 2 is fixed to the
maximum value or the minimum value, and the direct current does not flow into the power
amplifier 8 or the like. Even if the signal processing unit 1 and the PCM-PWM conversion unit 2
are operated by the auxiliary clock signal Sa, it is impossible to correctly process the PCM audio
data signal DI, so the amplitude from the PCM-PWM conversion unit 2 is Only PWM audio
signals Do and XDO whose levels are almost zero are output. Therefore, the user can quickly
recognize that the data shift clock signal SCK or the like has stopped due to the disconnection of
the signal line or the like. In this case, even if the data shift clock signal SCK is stopped and the
mute circuit is operated in the PCM-PWM converter 2 by the detection signal Sd in order to make
the amplitude levels of the PWM audio data signals DO and XDO completely 0. Good. FIG. 5 is a
circuit diagram showing a modification of FIG. Here, the third stage frequency division counter
33 is connected to the second stage frequency division counter 32 of the frequency divider 30 of
FIG. Another auxiliary clock signal Sa 'having a frequency close to the sampling frequency fs of
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the sampling signal SYN is output from the counter signal output terminal Q of the frequency
division counter 33. Furthermore, two OR elements 44, 45.1 NAND elements 46 and one inverter
47 are attached to the signal switching unit 4 of FIG.
Further, the auxiliary clock signal Sa 'is supplied to one input terminal of one of the OR elements
45. The inverted detection signal... Is supplied to the other input terminal of the one OR element
45 as in FIG. 3, and the circuit clock signal Sc and the circuit clock signal Sc are supplied to the
two input terminals of the other OR element 44. A detection signal Sd is supplied. That is, in the
signal switching unit 4 of FIG. 5, the output terminals are separately drawn from the two
inverters 43 1 and 47 2. In FIG. 5, in the case where the circuit clock signal Sc is generated based
on the sampling signal SYN instead of the data shift clock signal SCK, when the circuit clock
signal Sc is cut off, From the output side, it is possible to supply an auxiliary clock signal Sa
whose sampling is similar to the signal SYN. In this way, the operation of the signal processing
unit 1 and the PCM-PWM conversion unit 2 can be continued almost continuously by the
auxiliary clock signal Sa '. In the above modification (FIG. 5), the circuit clock signal Sc is
generated based on the sampling signal SYN instead of the data clock signal 5CKO by
appropriately selecting the two output terminals of the signal switching unit 4, and the DSP It
becomes possible to apply also to the audio reproduction circuit which is operating etc.
Furthermore, since the stop of the sampling signal SYN and the data shift clock signal SCK can be
detected at one time, the detection accuracy can be improved. As described above, according to
the present invention, the operation of the signal processing unit and the PCM-PWM conversion
unit is stopped due to the stop of the timing signal such as the data shift clock signal, which is
unnecessary for the power amplifier and the speaker. An audio reproduction circuit capable of
preventing direct current from flowing is realized. Therefore, there is no possibility that the
above-mentioned power amplifier and speaker will be destroyed.
[0002]
Brief description of the drawings
[0003]
FIG. 1 is a block diagram showing the principle configuration of the present invention, FIG. 2 is a
circuit diagram showing one embodiment of the present invention, FIG. 3 is a circuit diagram
showing a concrete example of the present embodiment, and FIG. FIG. 5 is a circuit diagram
showing a modification of FIG. 3, FIG. 6 is a block diagram showing a conventional audio
reproduction circuit, and FIG. 7 shows the operation of FIG. It is a timing chart for explaining.
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In the figure, 1 ... signal processing unit, 2 ... PCM-PWM conversion unit, 3 ... auxiliary clock
signal generation unit, 4 ... signal switching unit, 5 ... circuit clock signal disconnection detection
unit, 6 иии Circuit clock signal generation unit, 7 и и и Crystal oscillator, 8 и и и Power amplifier.
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