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DESCRIPTION JPH06152326

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DESCRIPTION JPH06152326
[0001]
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to
processing digital audio signals, and more particularly to digitally filtering stereo data in order to
improve the quality of audio information in an efficient manner. It is about (filtering).
[0002]
BACKGROUND OF THE INVENTION Many devices and methods are known for filtering image and
audio information in an efficient manner. U.S. Pat. No. 4,918,742 discloses an image processing
system which uses a single processor to perform image rotation.
[0003]
As another example of an image processing system, U.S. Pat. No. 4,823,299 discloses a real-time
system which processes a complex "Coleman filter" algorithm. This algorithm is used to process
radar signals in target tracking, and its application to audio information is unknown.
[0004]
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As another prior art, U.S. Pat. No. 4,947,362 discloses an adaptive digital filtering circuit for
signal processing implemented in a VLSI semiconductor chip. The adaptive digital filtering circuit
has two delay lines to generate a matrix of simultaneously sampled signals of both input and
output signals. The filter circuit uses parallel logic to operate the filter circuit to accommodate
the least mean square.
[0005]
As a final prior art, U.S. Pat. No. 4,117,541 discloses a configurable parallelarithmetic structure
for performing repetitive digital filtering operations. The present invention relates to processing
in which digital data emulated by six stages of six-order elliptical filters is time-division
multiplexed and frequency-division multiplexed.
[0006]
All the publications mentioned above neither suggest nor teach a method and apparatus using a
parallel digital filtering circuit to process audio information iteratively.
[0007]
SUMMARY OF THE INVENTION The main object of the present invention is to improve the
processing of digital audio signals by filtering stereo data in parallel using an iterative digital
filtering circuit. .
[0008]
SUMMARY OF THE INVENTION The filtering circuit of the present invention receives stereo
audio information through an analog input port of an audio subsystem.
This stereo audio information is digitized by an analog to digital converter (ADC) and transferred
to the "digital signal processor (DSP)" data space.
The data is filtered to provide anti-aliasing. This filtering operation processes stereo audio
information in parallel, resulting in machine cycle savings. The filtered signal is directed to the
compression process or, at the host computer, to the conversion process to another form.
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[0009]
Also, a filtering operation is required to regenerate the audio signal. The digitized audio signal
from the host computer is passed through a parallel iterative digital filtering circuit. Thereafter,
the digital signal filtered by the filtering circuit is converted into an analog signal by a digital
signal to analog signal converter (DAC) and then sent to a speaker, amplifier or other device.
[0010]
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A representative hardware
environment of a computer in accordance with the present invention having a central processing
unit 10, such as a conventional microprocessor, and a plurality of devices connected via a system
bus 12 is shown. It is shown in 1. The computer illustrated in FIG. 1 may be used to connect
peripheral devices such as disk devices 20 to random access memory (RAM) 14, read only
memory (ROM) 16, and system bus 12. / User interface adapter 22 for connecting other user
interface devices such as: / O adapter 18 with keyboard 24, mouse 26, speaker 28, microphone
32 and touch screen device (not shown) And a communication adapter 34 for connecting the
computer to the data processing network, and a display adapter 36 for connecting the display 38
to the system bus 12.
[0011]
FIG. 2 illustrates a block diagram of a digital audio subsystem 210 in accordance with the
present invention. Host computer 200 is shown in FIG. Audio system 210 is connected to the bus
of host computer 200 and includes a "digital signal processor (DSP)" 220 for operating the
repetitive digital filtering circuit in accordance with the present invention. Stereo data is input
from an analog signal to digital signal converter (ADC) 230 and transferred to a speaker or other
audio device via digital signal to analog signal converter (DAC) 240 Ru.
[0012]
When digital audio data is recorded or digital audio data is reproduced, the iterative digital
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filtering circuit is used to remove the effects of unwanted noise and to smooth the data. These
filtering operations are performed by a digital signal processor 220 such as a Texas Instruments
TMS320 digital signal processor (DSP).
[0013]
If stereo sound is included, a separate filtering circuit is used for each channel. Although the
filtration properties of each channel, including bandwidth and sample rate, are usually the same,
different filtration circuits are used because the channel conditions of each filtration circuit are
different.
[0014]
The equations that make up the 5-pole repetitive digital filter circuit for stereo processing of the
right and left channels are shown below.
[0015]
Right side channel: WR2 = GAIN1 * XNO + B2 * YN2 YN2 = YN1 YN1 = (WR2 + 2 * B1 * YN1) * 2
* 2 **-16 WR2 = GAIN2 * XN1 + B4 * YN4 YN4 = YN3 YN3 = (WR2 + 2 * B3 * YN3) * 2 * 2 ** 16YN5 = (GAIN3 * YN3 + B5 * YN5) * 2 * 2 **-16 Left channel: WR6 = GAIN1 * XNO2 + B2 *
YN22 YN22 = YN12 YN12 = (WR6 + 2 * B1 * YN12) * 2 * 2 **-16WR6 = GAIN2 * YN12 + B4 *
YN 42 Y N 42 = Y N 32 Y N 32 = (WR 6 + 2 * B 3 * Y N 32) * 2 * 2 **-16 Y N 52 = (GAIN 3 * Y N
32 + B 5 * Y N 52) * 2 * 2 **-16
[0016]
The following is a summary of the above equation:
1. For each channel, the filtration circuit is composed of two composite poles and one single pole.
2. To minimize errors due to fixed point arithmetic operations, the filter circuit coefficients (16
bits) for both channels are scaled as follows. That is, GAIN1, GAIN2, GAIN3, B2, B4 and B5 are
reduced by 2 ** 15, and B1 and B3 are reduced by 2 ** 14. 3. The numerical values for the
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special sample frequency of 44100 Hertz and the cut-off frequency of 7000 Hertz are as follows.
If not reduced: If reduced B1 0.7435 12182 B2-0.1991-6524 B3 0.8566 14035 B4-0.539917691 B5 0.3689 12088 GAIN1 0.4556 14929 GAIN2 0.6833 22390 GAIN3 0.6311 206804.
Processing is performed with saturation control turned on.
[0017]
A comparable arrangement for processing these filter circuits in a non-parallel manner is
functionally illustrated in FIG. In FIG. 3, the symbols GAIN1 to GAIN3 represent the gain of the
filter circuit, and the symbols B1 to B4 represent the filter circuit coefficients. Also, the ones with
"*", such as "GAIN 1 *" and "B 2 *", are the same for the right side channel and the left side
channel. The filter circuit gains “GAIN1” 400, “GAIN2” 402 and “GAIN3” 403 for each
channel, and the filter circuit coefficients “B1” to “B5” are different even if the values of
each channel are the same. Care must be taken to be loaded. This redundant loading of gains and
coefficients uses machine cycles with low efficiency. Although this particular example uses a five
pole filtration circuit, this process is kept independent of the size of the filtration circuit.
Inefficiencies increase with the size of the filter circuit.
[0018]
The IBM Digital Signal Processor (ISP) provides the parallel processing power used by the
present invention to significantly reduce processing time. Details of the ISP will be described
later. The structure for processing two-pole, five-pole repetitive digital filtration circuits in
parallel is shown in FIG. The filter circuit gain and filter coefficient for both channels are loaded
in one go. This process reduces the number of load processes required and, depending on the
parallel nature of the ISP, allows several special instructions to be performed simultaneously.
[0019]
5-12 illustrate the parallel nature of the processing structure according to the invention. The
process is divided into three sections: That is, (1) "right side channel processing" section for
processing unique introduction to right side channel, and (2) "left side channel" section for
processing unique installation to left side channel And (3) “Common processing” section to
process common instructions for both channels.
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[0020]
Several instructions appear on the same line throughout the entire structure. Instructions
generated on the same line are processed during the same cycle. This process reduces the overall
number of cycles required. Arranging filter circuits in this manner provides the opportunity to
exploit the parallel processing power of the ISP.
[0021]
The table below shows the ISP source code for processing two channels of stereo data in parallel
using a two pole, five pole digital filter circuit.
[0023]
This configuration reduces the processing requirements of the filtration circuit by more than 30
percent.
[0024]
IBM Signal Processor (ISP) Hardware Architecture The IBM Signal Processor (ISP) is a digital
signal processor that operates at 16 million instructions per second (MIPS).
The ISP has a "Harvard" architecture with a data address space that is completely separate from
the instruction address space.
[0025]
The ISP can address up to 64K instructions and up to 32K data words.
The instructions are 24 bits wide and the data words are 16 bits wide. The instruc- tion passes
through a three-phase pipeline of (1) Fetzsch Phase, (2) Decode Phase, and (3) Execution Phase.
The arithmetic logic unit (ALU) is a circuit separate from the multiplier, so that ALU arithmetic
and multiplication operations can occur simultaneously in a single machine cycle.
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[0026]
The introduction can be classified into the following two categories. That is, they are (1)
"Simplex" instructions and (2) "parallel" instructions. Single type instructions perform a single
operation, such as loading from memory, for one machine cycle. The operations in parallel
instructions are encoded as a single 24-bit instruction.
[0027]
ISP General Purpose Registers The ISP includes eight general purpose 16-bit registers, R0
through R7 (see FIG. 13). The resistors R2 and R6 have a 16 bit extension which can be used for
certain 32 bit operations. R0 and R4 are indices for forming a base displacement address for load
instructions, store instructions, store immediate instructions and most branch instructions. It can
be used as a register. Also, R0 and R4 can perform module addressing or circular addressing.
Module addressing is controlled by the setting of a bit in the machine control register. R4 can
perform table addressing but not R0. The register R5 (also called RX) is always one of the data
sources at the time of multiplication. R1, R3 and R7 do not have special properties. R7 is usually
used to store the return address for subroutine calls.
[0028]
As shown in FIG. 13, the general purpose registers are arranged in two banks, R0 to R3 and R4 to
R7. In a load instruction or a composite instruction including an immediate load instruction, the
transfer target and the ALU operation target must come from the opposite register bank. The ISP
can multiply two 16-bit numbers in one machine cycle. The product of this multiplication is
stored in a 32-bit multiplier product (Register Product-RP) register. The RP register can be used
to perform a 32-bit addition to WR2 or WR6. The low order bit of the product can be accessed as
register RPL, and the high order 16 bits can be accessed as register RPH.
[0029]
The machine control register shown in FIG. 14 is a register that controls various functions in the
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IPS processor. This machine control register is divided into two 16 bit registers, MCRH and
MCRL registers. The following is a list of MCRH register bits.
[0031]
The ISP program makes extensive use of MCRH registers to control modular addressing,
mathematical saturation and scaling of multipliers. The eight low order bits in the MCRL register
are used to activate or inhibit the interrupt levels, 0-7. The Instruction Link Register (ILR) is
usually equal to the Location Counter. Also, this register protects the location counter after an
interrupt and is used to perform position related branches. The "Common Data Bus (RCDB)"
register is used implicitly by all data transfer operations. The RCDB register usually holds the last
value loaded or stored. The RCDB registers are collated for the following reasons. Some branch
instructions take the new contents of the location counter from the RCDB register, and tests and
branches can be performed for specific bits in the RCDB register.
[0032]
Referring to FIG. 15, the process status register is shown. The processing status register is
composed of two 16-bit registers, PSRH and PSRL registers. The following is a list of PSRH
register bits.
[0034]
The PSRH register is normally accessed only during interrupt processing. The PSRH register is
often accessed implicitly because it contains the status code or status flag for the chip of the ISP.
PSRLレジスタは、ISPのプログラマによつてアクセスされてはならない。 The Indirect
Program Access Register (RIPA) is used when loading data from the instruction's address space
with the Indirect Program Access instruction.
[0035]
ISP addressing is a word addressable architecture. At all times, 16 bits are read from memory
and only even addresses are accessible. Indexed addressing is performed using the R0 and R4
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index registers. The contents of the register are combined with the 8-bit or 16-bit offset. There
are offset limitations depending on whether a single type of instruc- tion was used or a parallel
type of instruc- tion was used. Also, circular addressing is activated via modulo N addressing
using the R0 and R4 registers. However, the buffer has to be aligned and dimensioned by two
folds. Also, table addressing is performed using the R4 register.
[0036]
Instructions in the ISP pass through the three phase pipeline. Phase 1 is a take-out operation.
Phase 2 is a decoding operation. Phase 3 is an execution operation. Three operations occur
simultaneously during each machine cycle. The instructions are retrieved from the instruction
memory. The previously retrieved instructions are decoded including the resolution of the
operands and the address. The previously decoded instructions are executed. The net effect is
that the throughput of the instruction is one instruction per machine cycle. Most instructions run
at the end of the phase 3. However, the branch instruction runs at the end of phase 2 and there is
no additional hardware activity during phase 3. The instruction immediately following the branch
instruction is fetched between the same phases as the branch is decoded and executed. The
instructions immediately after the branch are always executed.
[0037]
The present invention provides a digital filtering circuit for iteratively processing audio
information in parallel.
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