close

Вход

Забыли?

вход по аккаунту

?

DESCRIPTION JPH08154291

код для вставкиСкачать
Patent Translate
Powered by EPO and Google
Notice
This translation is machine-generated. It cannot be guaranteed that it is intelligible, accurate,
complete, reliable or fit for specific purposes. Critical decisions, such as commercially relevant or
financial decisions, should not be based on machine-translation output.
DESCRIPTION JPH08154291
[0001]
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a
level compression circuit suitable for application to, for example, a speaker apparatus with a
built-in amplifier.
[0002]
2. Description of the Related Art It is known in the prior art to provide a level compression circuit
in front of a speaker in order to prevent an excessive input to the speaker in an amplifier built-in
speaker device.
[0003]
FIG. 5 shows the configuration of a conventional level compression circuit.
In the figure, 1a and 1b are input terminals, and an input voice signal ei is supplied between the
input terminals 1a and 1b. The input terminal 1 b is grounded, and the input terminal 1 a is
grounded via a series circuit of a resistor 3, a resistor 4 and a collector-emitter of an NPN
transistor 5 constituting the voltage dividing circuit 2. Then, the output terminal 6a is derived
from the output terminal of the voltage dividing circuit 2, that is, the connection point of the
resistor 3 and the resistor 4, and the output terminal 6b is grounded. In this case, in the voltage
dividing circuit 2, the audio signal ei is divided by the series impedance of the resistor 3 and the
10-04-2019
1
collector-emitter of the resistor 4 and the transistor 5, and the divided signal is between the
output terminals 6a and 6b. It is output as an output audio signal vo.
[0004]
Further, the divided signal output from the voltage dividing circuit 2, that is, the audio signal vo
is amplified by the amplifier circuit 7 and then supplied to the peak rectifier circuit 8. That is, the
output terminal of the amplifier circuit 7 is grounded via a series circuit of the anode / cathode
of the diode 9 and the capacitor 10. Further, the output terminal of the peak rectification circuit
8, that is, the connection point of the diode 9 and the capacitor 10 is connected to the base of the
transistor 5 via the resistor 11, and the peak rectification signal PD is supplied to the base of the
transistor 5 as a control signal. .
[0005]
In the above configuration, assuming that the resistance values of the resistors 3 and 4 are R1
and R2 and the impedance value between the collector and emitter of the transistor 5 is Rx, the
level of the input voice signal ei is small and the peak rectified signal PD is approximately 0.
When 6 V or less, since Rx >> R1 and R2, the output voice signal vo becomes substantially equal
to the input voice signal ei. However, when the level of the input audio signal ei increases and the
peak rectified signal PD exceeds 0.6 V, the impedance value Rx between the collector and the
emitter of the transistor 5 decreases exponentially exponentially. The level compression
operation according to the second embodiment limits the level increase of the output voice signal
vo.
[0006]
The solid line a in FIG. 6 shows the level compression characteristics of the level compression
circuit of the example of FIG. E1 is an input signal level (compression start input level) for the
peak rectified signal PD to be about 0.6 V, and E2 is an input signal level for the peak rectified
signal PD to be a voltage for saturating the transistor 5. In this case, the level compression range
is in the range of E1 to E2, but this level compression range depends on the value of R1 / R2, and
the larger the value of R1 / R2, the wider the level compression range. Also, the compression
ratio depends on the magnitude of the value of R2. The broken line b in FIG. 6 indicates the input
/ output characteristics in the case where the level compression control described above is not
10-04-2019
2
performed with the transistor 5 in the off state.
[0007]
By the way, the level compression circuit of the example of FIG. 5 has a problem that nonlinear
distortion occurs in the output signal due to the nonlinearity of the transistor 5 in the level
compression range. If the compression start input level E1 is made much lower by raising the
gain of the amplifier circuit 7 etc., the above-mentioned non-linear distortion can be kept
sufficiently small, but in that case there is a problem such as deterioration of the SN ratio It
occurs.
[0008]
Therefore, the present invention provides a level compression circuit that can reduce non-linear
distortion without causing deterioration of the SN ratio.
[0009]
According to a first aspect of the present invention, there is provided a level compression circuit
which divides a voltage by means of a first resistor and a combined impedance of a second
resistor and a series circuit of collector and emitter of a transistor. The transistors forming the
one and the other of the two voltage dividing means are respectively an NPN transistor and a
PNP transistor, and the input signal is supplied to one and the other voltage dividing means to
divide the voltage. The divided signals output from the other voltage dividing means are added
by the adding means, and the added signal output from the adding means is as it is or amplified
and then supplied to the first and second peak rectifying means for peak rectification. A peak
rectified signal of positive polarity outputted from the first peak rectifying means is supplied as a
control signal to the base of the NPN transistor constituting one voltage dividing means. And the
peak rectified signal of negative polarity outputted from the second peak rectifying means is
supplied as a control signal to the base of the PNP type transistor constituting the other voltage
dividing means, and the added signal outputted from the adding means is outputted as an output
signal It is characterized by being.
[0010]
According to the first aspect of the invention, since the control signal corresponding to the
output signal level is supplied to the bases of the transistors of the one and the other voltage
dividing means to control the impedance, the input signal is controlled by each voltage dividing
means. Level compression control is performed according to the level, and the output signal
10-04-2019
3
output from the addition means is subjected to level compression control.
[0011]
In this case, non-linear distortion occurs in the voltage division signals output from one and the
other voltage dividing means in the level compression range due to non-linearity of the
transistor.
However, since NPN type and PNP type transistors are respectively used as transistors
constituting one and the other voltage dividing means, the dominant even number included in
the voltage dividing signal outputted from these one and the other voltage dividing means The
second harmonic distortion components are opposite in polarity to each other, and are canceled
out by the addition processing in the addition means.
[0012]
Therefore, the output signal output from the addition means is only the odd harmonic distortion
component other than the fundamental wave component, and it is possible to significantly reduce
the non-linear distortion caused by the non-linearity of the transistor in the level compression
range. Become.
In addition, as in the prior art, the compression start input level is lowered to keep nonlinear
distortion small, and the deterioration of the SN ratio is not caused.
[0013]
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of a level
compression circuit according to the present invention will be described below with reference to
FIG.
This example is an example applied to level compression control of an audio signal. In FIG. 1,
parts corresponding to those in FIG. 5 are given the same reference numerals.
10-04-2019
4
[0014]
In the figure, 1a and 1b are input terminals, and an input voice signal ei is supplied between the
input terminals 1a and 1b. The input terminal 1b is grounded. The input terminal 1a is grounded
via a series circuit of a resistor 3A constituting a voltage dividing circuit 2A, a resistor 4A and a
collector-emitter of an NPN transistor 5A. Further, the input terminal 1a is grounded via a series
circuit of a resistor 3B constituting a voltage dividing circuit 2B, a resistor 4B and a collectoremitter of a PNP transistor 5B. In this case, when the resistances of the resistors 3A and 4A of
the voltage dividing circuit 2A are set to R1 and R2, respectively, the resistances of the resistors
3B and 4B of the voltage dividing circuit 2B are also set to R1 and R2, respectively.
[0015]
The output terminal of the voltage dividing circuit 2A, that is, the connection point between the
resistors 3A and 4A, is connected to one input terminal of the mixing circuit 12 constituting the
adding means, and the output terminal of the voltage dividing circuit 2B and thus the resistors
3B and 4B. The connection point is connected to the other input terminal of the mixing circuit
12. Then, the output terminal 6a is derived from the output side of the mixing circuit 12, and the
output terminal 6b is grounded.
[0016]
In this case, in the voltage dividing circuit 2A, the input audio signal ei is divided by the series
impedance of the resistor 3A and the collector-emitter of the resistor 4A and the transistor 5A. In
the voltage dividing circuit 2B, the input audio signal ei is divided by the series impedance of the
resistor 3B and the collector-emitter of the resistor 4B and the transistor 5B. The mixing circuit
12 performs addition processing (mixing processing) of the voltage division signal va output
from the voltage division circuit 2A and the voltage division signal vb output from the voltage
division circuit 2B, and the addition signal is output terminal 6a. , 6b are output as an output
voice signal vo.
[0017]
10-04-2019
5
The addition signal output from the mixing circuit 12, that is, the output audio signal vo is
amplified by the amplifier circuit 7 and then supplied to the peak rectification circuit 8A. That is,
the output terminal of the amplifier circuit 7 is grounded via a series circuit of the anode /
cathode of the diode 9A and the capacitor 10A. The output terminal of the peak rectification
circuit 8A, that is, the connection point of the diode 9A and the capacitor 10A is connected to the
base of the transistor 5A constituting the voltage dividing circuit 2A via the resistor 11A, and the
peak rectification signal PDa of positive polarity is controlled. The signal is supplied to the base
of the transistor 5A.
[0018]
Further, the addition signal output from the mixing circuit 12, that is, the output audio signal vo
is amplified by the amplifier circuit 7 and then supplied to the peak rectification circuit 8B. That
is, the output terminal of the amplifier circuit 7 is grounded via a series circuit of the cathodeanode of the diode 9B and the capacitor 10B. The output terminal of the peak rectification circuit
8B, that is, the connection point between the diode 9B and the capacitor 10B is connected to the
base of the transistor 5B constituting the voltage dividing circuit 2B via the resistor 11B, and the
negative peak rectification signal PDb is controlled. The signal is supplied to the base of the
transistor 5B.
[0019]
In the above configuration, in the voltage dividing circuit 2A, assuming that the resistances of the
resistors 3A and 4A are R1 and R2 respectively and the impedance value between the collector
and emitter of the transistor 5A is Rxa, the level of the input audio signal ei is small and peak
rectification is performed. When the signal PDa is about 0.6 V or less, Rxa >> R1 and R2, and
therefore the divided voltage signal va becomes substantially equal to the input audio signal ei.
However, when the level of the input audio signal ei increases and the peak rectified signal PDa
exceeds 0.6 V, the impedance value Rxa between the collector and emitter of the transistor 5A
exponentially decreases rapidly, so the voltage dividing circuit 2A The level compression
operation according to the above limits the increase in level of the positive voltage division signal
va.
[0020]
10-04-2019
6
In the voltage dividing circuit 2B, when resistances of the resistors 3B and 4B are R1 and R2 and
an impedance value between the collector and emitter of the transistor 5B is Rxb, the level of the
input audio signal ei is small and the peak rectified signal PDb is When the absolute value is
about 0.6 V or less, Rxb >> R1 and R2, and therefore the divided signal vb becomes substantially
equal to the input audio signal ei. However, when the level of the input audio signal ei increases
and the absolute value of the peak rectified signal PDb exceeds 0.6 V, the impedance value Rxb
between the collector and emitter of the transistor 5B exponentially decreases rapidly. The level
compression operation by the pressure circuit 2B limits the increase in level of the positive
voltage division signal vb.
[0021]
Therefore, the output audio signal vo output from the mixing circuit 12 as an addition signal of
the voltage division signal va and the voltage division signal vb is subjected to level compression
control as in the example of FIG. 5 (indicated by solid line a in FIG. 6). See the level compression
characteristics shown).
[0022]
By the way, non-linear distortion occurs in the voltage division signals va and vb output from the
voltage dividing circuits 2A and 2B due to non-linearity of the transistors 5A and 5B in the level
compression range, respectively. The audio signal vo is such that nonlinear distortion is greatly
reduced.
[0023]
FIG. 2 shows the principle of reduction of nonlinear distortion.
As the non-linearity of the transistors 5A and 5B, second-order non-linearity is assumed as shown
by a solid line a and an alternate long and short dash line b in FIG. 2B, respectively.
In this case, the second-order non-linearity of the transistors 5A and 5B is completely
symmetrical about the origin (0, 0). The solid line c in FIG. 2B is a characteristic obtained by
combining the second-order non-linearity of the transistors 5A and 5B and is a straight line.
10-04-2019
7
[0024]
When an input audio signal ei (positive polarity signal) as shown by the solid line d in FIG. 2A is
supplied to the voltage dividing circuit 2A, the voltage division signal va is expanded on the
positive side as shown by the solid line e in FIG. The signal is compressed on the negative side to
become a positive signal having asymmetric waveform distortion. Further, when the input audio
signal ei is supplied to the voltage dividing circuit 2B, the voltage dividing signal vb is
compressed on the positive side and expanded on the negative side as shown by the alternate
long and short dash line f in FIG. It becomes a signal of the positive polarity which it has.
Therefore, the output sound signal vo output from the mixing circuit 12 is a signal from which
asymmetric waveform distortion has been removed as shown by the solid line g in FIG. 2C.
[0025]
By the way, in the reduction principle of FIG. 2, second-order non-linearity is assumed as the nonlinearity of the transistors 5A and 5B. In that case, only even-order harmonic distortion occurs as
non-linear distortion. However, the transistors 5A and 5B do not have perfect second-order nonlinearity in fact, and odd-order harmonic distortion also occurs in addition to the even-order
harmonic distortion mainly involved as the above-mentioned nonlinear distortion. In this case,
since the transistors 5A and 5B are respectively NPN type and PNP type, even-order harmonic
distortion components generated in the positive voltage dividing signals va and vb have opposite
polarities to each other, and the addition processing of the mixing circuit 12 It is offset by.
Therefore, the output sound signal vo output from the mixing circuit 12 is only the fundamental
wave component and the odd harmonic distortion component, and the nonlinear distortion is
reduced.
[0026]
For example, when the input audio signal ei is a sine wave signal of positive polarity of Eisin ωt,
the voltage division signal va of positive polarity output from the voltage dividing circuit 2A is
expressed by equation (1). Here, Ei is the amplitude of the sine wave signal, V1 is the amplitude
of the fundamental wave component, V2, V3, V4, ... are the amplitudes of second-, third-, fourthorder, ... harmonic distortion components, respectively. .phi.2, .phi.3, .phi.4,... indicate phase
angles of second-, third-, fourth-order harmonic distortion components, respectively.
10-04-2019
8
[0027]
va = V1 sin ωt + V2 sin (2ωt + φ2) + V3 sin (3ωt + φ3) + V4 sin (4ωt + φ4) + V5 sin (5ωt +
φ5) + (1) At this time, assuming that the equation (1) uses an NPN transistor, PNP The voltage
division signal vb of positive polarity outputted from the voltage dividing circuit 2B using the Ntype transistor is expressed by equation (2), with the polarity of only even-order harmonic
distortion component of equation (1) being inverted. .
[0028]
vb = V1 sin ωt−V2 sin (2ωt + φ2) + V3 sin (3ωt + φ3) −V4 sin (4ωt + φ4) + V5 sin (5ωt +
φ5) − (2) Therefore, the output obtained by adding the divided signals va and vb in the mixing
circuit 12 The audio signal vo is expressed as in equation (3).
That is, even-order harmonic distortion components are canceled out, and only the fundamental
wave component and the odd-order harmonic distortion components are obtained.
[0029]
vo = 2 V 1 sin ω t + 2 V 3 sin (3 ω t + φ 3) + 2 V 5 sin (5 ω t + φ 5) + 2 V 7 sin (7 ω t + φ 7) +
... (3) Thus, according to this example, the output voice signal vo output from the mixing circuit
12 is a fundamental wave component and an odd number Only the second harmonic distortion
component is generated, and non-linear distortion caused by non-linearity of the transistors 5A
and 5B constituting the voltage dividing circuits 2A and 2B can be reduced in the level
compression range. Here, odd-order harmonic distortion is smaller than even-order harmonic
distortion, and even-order harmonic distortion components can be canceled to significantly
reduce the total harmonic distortion rate.
[0030]
Curve a in FIG. 3 shows an example of measurement of distortion characteristics in the
embodiment of FIG. 1 in the case of having level compression characteristics as shown by solid
line a in FIG. 4 (broken line b in FIG. Input / output characteristics). The solid line b in FIG. 3 is an
example of measurement of distortion characteristics in the conventional example of FIG. As
apparent from FIG. 3, the embodiment can significantly reduce the total harmonic distortion
10-04-2019
9
factor. The level compression characteristic and the distortion characteristic hardly change in the
audio frequency range.
[0031]
In the above embodiment, the addition signal output from the mixing circuit 12 is amplified by
the amplifier circuit 7 and then supplied to the peak rectification circuits 8A and 8B. However,
depending on the level of the addition signal, the addition signal may be added It is also
conceivable to supply the peak rectification circuits 8A and 8B directly after supplying them to
the peak rectification circuits 8A and 8B or damping control of the levels. Further, although the
example in which the present invention is applied to level compression control of an audio signal
has been shown in the above embodiment, it is of course possible to apply to level compression
control of other signals.
[0032]
According to the invention of claim 1, since the NPN transistor and the PNP transistor are
respectively used as the transistors constituting the one and the other voltage dividing means to
which the input signal is supplied, these one and the other The even-order harmonic distortion
components included in the voltage-divided signal output from the voltage-dividing means are
opposite in polarity to each other, and are canceled out by the addition process in the adding
means. Therefore, the output signal output from the addition means is only the odd harmonic
distortion component other than the fundamental wave component, and the nonlinear distortion
caused by the non-linearity of the transistor in the level compression range can be significantly
reduced, and the conventional Thus, the compression start input level is lowered to keep
nonlinear distortion small, and the deterioration of the SN ratio is not caused.
[0033]
Brief description of the drawings
[0034]
1 is a block diagram showing an embodiment of the level compression circuit according to the
present invention.
10-04-2019
10
[0035]
It is a figure which shows the reduction principle of the nonlinear distortion of the FIG. 2
Example.
[0036]
It is a figure which shows the measurement example of the distortion characteristic of FIG. 3
Example and a prior art example.
[0037]
It is a figure which shows the example of the level compression characteristic of FIG. 4 Example.
[0038]
5 is a block diagram showing a conventional level compression circuit.
[0039]
6 is a diagram showing an example of the level compression characteristics.
[0040]
Explanation of sign
[0041]
DESCRIPTION OF SYMBOLS 1a, 1b Input terminal 2A, 2B Voltage dividing circuit 3A, 3B, 4A, 4B
Resistor 5A NPN type transistor 5B PNP type transistor 6a, 6b Output terminal 7 Amplifier
circuit 8A, 8B Peak rectifier circuit 12 Mixing circuit
10-04-2019
11
Документ
Категория
Без категории
Просмотров
0
Размер файла
21 Кб
Теги
description, jph08154291
1/--страниц
Пожаловаться на содержимое документа