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DESCRIPTION JPH10335956

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DESCRIPTION JPH10335956
[0001]
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a
method and apparatus for controlling the volume of a 1-bit digital signal obtained by delta sigma
modulation.
[0002]
2. Description of the Related Art In 1-bit digital signals obtained by delta sigma modulation, each
bit has an equal weight, and an effective frequency band and a dynamic range, which are
opposite characteristics, are arbitrarily matched with the type of sound source etc. It can be set
and is actively researched for next-generation audio. As a typical prior art for controlling the
reproduction volume of this 1-bit digital signal, there is, for example, JP-A-6-335082 previously
proposed by the present applicant.
[0003]
In this prior art, a bit clock synchronized with a 1-bit digital signal is integrated to create a
triangular wave, and the triangular wave and a variable reference voltage are compared by a
comparator to generate a pulse train having a variable pulse width. The pulse width of the 1-bit
digital signal is controlled by ANDing the 1-bit digital signal with the 1-bit digital signal to
perform volume control.
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[0004]
The above-mentioned prior art volume control method has the problem that the reference
voltage to be input to the comparator needs to have high accuracy.
That is, when the accuracy is low, the pulse width is not constant, and when the 1-bit digital
signal is reproduced in this state, it appears as noise.
[0005]
An object of the present invention is to provide a method and apparatus for controlling the
volume of a 1-bit digital signal which can control the volume with high precision without
generating noise.
[0006]
A method of controlling the volume of a 1-bit digital signal according to the present invention
synchronizes the 1-bit digital signal obtained by delta sigma modulation with the 1-bit digital
signal, And volume control is performed by controlling the pulse width of the 1-bit digital signal
using a clock signal of a predetermined integer multiple.
[0007]
According to the above configuration, when the sampling frequency of the 1-bit digital signal is
fs, the pulse width of the 1-bit digital signal is converted, that is, duty control is performed using
a sufficiently high clock signal of 16 fs or 32 fs, for example.
[0008]
Therefore, an error in the pulse width can be guaranteed with high accuracy of the crystal
oscillator which is the clock signal source, and the pulse width can be controlled in the step
corresponding to the clock frequency, for example, the clock frequency is 16fs. Sometimes the
pulse width can be controlled in steps of approximately 6% of the period of a 1-bit digital signal,
and when the clock frequency is 32 fs, control can be performed in steps of approximately 3%;
And the volume can be controlled with high accuracy.
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Furthermore, the determination threshold of the pulse width is determined by the count value of
the clock pulse, so that threshold fluctuation does not occur, stable operation can be performed,
and noise does not occur.
[0009]
The volume control method of a 1-bit digital signal according to the invention of claim 2 is
characterized in that the maximum value of the pulse width is less than the sampling period of
the 1-bit digital signal.
[0010]
According to the above configuration, even if the input 1-bit digital signal includes continuous
portions of "1" or "0", the + 1-bit digital signal and the -1-bit digital signal output are the one-bit
digital signal. Since it always switches from "1" to "0" within the sampling period of the signal,
the pulse width error due to waveform rounding or the like occurring at the rising and falling of
the pulse alternates with the case where the same data continues The case can be made equal,
and the volume can be controlled with higher accuracy.
[0011]
Furthermore, the volume control method of a 1-bit digital signal according to the invention of
claim 3 is characterized in that the volume control is performed by controlling the peak value of
the 1-bit digital signal obtained by delta sigma modulation.
[0012]
According to the above configuration, it is possible to stably perform high-accuracy volume
control with a simple configuration such as a variable gain amplifier, as opposed to the abovedescribed complicated configuration for pulse width control.
[0013]
Further, the volume control method of a 1-bit digital signal according to the invention of claim 4
is characterized in that the volume control shown in claim 1 or 2 and the volume control shown
in claim 3 are continuously executed mutually. Volume control method of 1-bit digital signal.
[0014]
According to the above configuration, the method according to claim 1 or 2, wherein the volume
is controlled discretely at predetermined steps determined by the clock frequency, and the power
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element will be used in the unsaturated region. By combining the method described in item 3, the
volume control in minute steps can be performed with high power efficiency.
[0015]
Furthermore, according to the volume control method of a 1-bit digital signal according to the
invention of claim 5, it is preferable that the output + 1-bit digital signal and the -1-bit digital
signal be signals of only "0" when silence or muting. It features.
[0016]
According to the above configuration, the pulse width control output shown in claim 1 or 2 and
the peak value control output shown in claim 3 are respectively connected via the buffer and the
inverter parallel to each other for the subsequent differential input amplifier. Since the outputs
obtained are mutually opposite phases of +1 bit digital signal and -1 bit digital signal, when the
demodulated analog audio signal is silent level, the output +1 bit digital signal and -1 bit digital
signal are originally , "0" should be a signal only.
[0017]
Therefore, even if there is a continuous portion of "0" or "1" due to quantization noise in the
input 1-bit digital signal, the output +1 bit digital signal and -1 bit digital signal are forced to be
"0" only. By forming a signal sequence, the quantization noise can be removed from the
demodulated analog speech signal.
Further, in the configuration shown in claim 4, either of two pulse width control outputs of the
+1 bit digital signal and the −1 bit digital signal, that is, a peak value control input or a peak
value control output from two amplifiers, The same effect can be obtained by forcing the signal
sequence to be "0" only.
[0018]
In the sound volume control method of a 1-bit digital signal according to the invention of claim 6,
when silence or muting is performed, the input 1-bit digital signal is a signal that alternately
repeats "0" and "1". It features.
[0019]
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According to the above configuration, when the demodulated analog audio signal is at the silent
level, the 1-bit digital signal of the input should be an alternating signal of "0" and "1".
[0020]
Therefore, even if there is a continuous portion of "0" or "1" due to quantization noise in the 1-bit
digital signal of the input, the 1-bit digital signal actually input is forced to "0" and "1". And the
quantization noise can be removed from the demodulated analog voice signal by making the
signal sequence of repeating.
[0021]
Furthermore, the volume control apparatus for a 1-bit digital signal according to the invention of
claim 7 performs counting operations when the 1-bit digital signal obtained by delta sigma
modulation is “1” and “0”. A clock signal source synchronized with the 1-bit digital signal
and generating a clock signal of a predetermined integer multiple to cause the first and second
counters to perform counting operations; First and second comparators for respectively
comparing the count values of the first and second counters with a value corresponding to a
desired volume setting value, and outputting a pulse width control signal when both are in
agreement; When the 1-bit digital signal becomes "1" and "0", output of the pulse is started, and
when the pulse width control signal is input, the output of the pulse is output. Characterized in
that it comprises a first and second flip-flops to be stopped.
[0022]
According to the above configuration, the input 1-bit digital signal is approximately 6% and 32 fs
when the clock frequency is 16 fs when the sampling frequency of the 1-bit digital signal is fs,
for example, a step corresponding to the clock frequency. Sometimes the pulse width can be
controlled in approximately 3% steps, the pulse width error can be guaranteed with high
accuracy of the crystal oscillator, and the volume can be controlled in small steps.
Further, the determination of the pulse width, that is, the reset of the output pulse is performed
in response to the count values of the first and second counters, and corresponds to the volume
set value which is a cabinet value for determining the pulse width. There is no undesired
variation of the value, so stable operation can be performed and noise generation can be
prevented.
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[0023]
Further, in the volume control device for a 1-bit digital signal according to the invention of claim
8, all the high-order values are set as values corresponding to the volume set value so that the
pulse width is less than the sampling period of the 1-bit digital signal. When the bit is "1", the
least significant bit is set to "0".
[0024]
According to the above configuration, at least the period of about 6% when the clock frequency is
16 fs and at least about 3 when the clock frequency is 32 fs with respect to the sampling period
of the 1-bit digital signal. The period of% is the pulse interval.
Therefore, the pulse width error due to waveform rounding or the like occurring at the rising and
falling of the pulse can be equal between the case where the same data continues and the case
where it alternates, and the volume can be controlled with higher accuracy. it can.
[0025]
Furthermore, in the volume control device for a 1-bit digital signal according to the invention of
claim 9, the 1-bit digital signal obtained by delta sigma modulation is input, and the pulse of the
1-bit digital signal is adapted to a desired volume setting value. It is characterized in that it
comprises a variable gain amplifier which amplifies and outputs with the above gain.
[0026]
According to the above configuration, it is possible to stably perform high-accuracy volume
control with the above-described complicated configuration for pulse width control by the gain
variable amplifier with the simple configuration.
[0027]
Further, the volume control apparatus for 1-bit digital signal according to the invention of claim
10 connects the volume control apparatus shown in claim 7 or 8 and the volume control
apparatus shown in claim 9 in cascade. It features.
[0028]
According to the above configuration, the configuration according to claim 7 or 8, wherein the
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volume can be controlled discretely at predetermined steps determined by the clock frequency,
and using the power element in the unsaturated region By combining with the configuration
shown in claim 9, the volume control in minute steps can be performed with high power
efficiency.
[0029]
DESCRIPTION OF THE PREFERRED EMBODIMENTS The first embodiment of the present
invention will be described below with reference to FIGS.
[0030]
FIG. 1 is a block diagram showing an electrical configuration of a pulse width control circuit 1
which is a sound volume control apparatus according to a first embodiment of the present
invention.
In the pulse width control circuit 1, the pulse width control signal generation circuit 2 generates
the 1-bit signal DA (substantially the same as the 1-bit signal DAT obtained by delta sigma
modulation) output from the flip flop 8 based on the bit clock BCK. , In a step corresponding to
the clock frequency of the clock signal source 3, converted into a pulse width corresponding to
the desired volume value set by the volume setting means 4, and the pulse width controlled +1
from the flip flops 6, 7 It is a circuit for outputting a bit signal DAT + and a -1 bit signal DAT-.
The +1 bit signal DAT + is a signal that becomes a predetermined high level when the 1 bit signal
DAT is "1", whereas the -1 bit signal DAT- is a signal that the 1 bit signal DAT is "1". When it is 0
′ ′, it is a signal that becomes the predetermined high level.
[0031]
The +1 bit signal DAT + and the -1 bit signal DAT- are demodulated into a volume-controlled
analog audio signal by passing through a low pass filter in the form of differential input.
Further, for example, in the configuration shown in the above-mentioned Japanese Patent
Application Laid-Open No. 6-335082, the +1 bit signal DAT + is applied to the switching element
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interposed between the + side power supply provided in the output stage and the terminal of the
speaker. Control the ON / OFF of the switching element, and also control the ON / OFF of the
switching element interposed between the + side power supply and the terminal of the speaker,
and thus the demodulated analog voice You can control the playback volume of.
[0032]
FIG. 2 is a block diagram showing a specific configuration of the pulse width control signal
generation circuit 2.
The 1-bit signal DA is input to the counter 11 as an enable signal.
The counter 11 counts clock pulses of the system clock CK from the clock signal source 3 when
the 1-bit signal DA is input.
The system clock CK is synchronized with the 1-bit signal DA (DAT), and its clock frequency is an
integral multiple of the frequency of the 1-bit signal DA (DAT). In the example shown in FIG. The
sampling frequency fs of (DAT) is selected to be 16 fs.
Therefore, the count value CNT of the counter 11 is input to the data comparison circuit 12 as 4bit data of C1, C2, C3 and C4.
[0033]
The data comparison circuit 12 also receives a 4-bit volume control signal VOLCTL of B1, B2, B3
and B4 from the volume setting means 4.
When the count value CNT of the counter 11 matches the set value of the volume control signal
VOLCTL, the data comparison circuit 12 outputs the pulse width control signal PWCTL + as an
active output.
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[0034]
Two systems as shown in FIG. 2 are provided in the pulse width control signal generation circuit
2, and an inverted output of the flip flop 8 to which the 1-bit signal DAT is input is provided in
another system not shown. The inverted signal / DA (see FIG. 1), which is an input signal, causes
the pulse width control signal PWCTL− to be an active output.
[0035]
Referring to FIG. 1, the pulse width control signals PWCTL + and PWCTL− are input to the clear
terminals of the flip flops 6 and 7, respectively.
The flip-flop 6 takes "1" of the 1-bit signal DAT based on the bit clock BCK, and the flip-flop 7
takes "1" of the inverted signal / DAT obtained by inverting the 1-bit signal DAT from the buffer
5 based on the bit clock BCK. Incorporate
Therefore, in the state where the pulse width control signal PWCTL + is inactive, the flip flop 6
makes the output +1 bit signal DAT + high when the 1 bit signal DAT is high level, and then the
pulse width control signal PWCTL + When activated, the +1 bit signal DAT + is set to low level.
On the other hand, when the pulse width control signal PWCTL- is inactive and the inversion
signal / DAT is at high level, the flip-flop 7 sets the output -1 bit signal DAT- to high level, and
then When the pulse width control signal PWCTL- becomes active, the -1 bit signal DAT- is set to
a low level.
[0036]
FIG. 3 is a waveform diagram for explaining the operation of the pulse width control circuit 1
configured as described above, and only a waveform relating to the +1 bit signal DAT + is shown
to simplify the description.
With respect to the 1-bit signal DA shown in FIG. 3A, the clock signal source 3 is synchronized in
timing as shown in FIG. 3B and when the sampling frequency of the 1-bit signal DAT is fs: A pulse
is generated every T / 16 with respect to the cycle T of 16 fs, that is, the 1-bit signal DAT, and is
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output to the pulse width control signal generation circuit 2 as the system clock CK.
[0037]
The pulse width control signal generation circuit 2 counts the pulses of the system clock CK in
the counter 11, and the count value CNT is a value set by the volume control signal VOLCTL (in
the example of FIG. When it becomes "7" level, as shown in FIG. 3C, the pulse width control signal
PWCTL + is made low active.
As a result, as shown in FIG. 3D, the flip-flop 6 in which the +1 bit signal DAT + is set to “1” by
incorporating “1” of the 1 bit signal DAT changes the +1 bit signal DAT + to “0”. Stop at
[0038]
Further, the volume setting means 4 sets the least significant bit B4 to "0" when all the upper bits
B1 to B3 of the volume control signal VOLCTL are "1".
For example, in the case where the input 1-bit signal DAT is a signal string of "010" and the
signal string of "0110", the ratio of the power component of 1 is 1: 2, but the rise of the pulse is
Also, due to the waveform rounding at the time of falling, the ratio of the power components is
not 1: 2, and the rounding of the waveform appears as noise.
On the other hand, the power component ratio can be maintained exactly at 1: 2 by preventing
all the bits B1 to B4 from becoming 1 as described above.
[0039]
That is, even if the input 1-bit signal DAT is a continuous signal of "1" as shown in FIG. 3 (e), the
+1 bit signal DAT + to be output has a period T as shown in FIG. 3 (f). Since it necessarily falls to
“0” in the inside, the influence of the waveform rounding at the rise and fall of the +1 bit
signal DAT + repeats the “1” continuous signal and “1” and “0” alternately. The influence
can be ignored, and the pulse width of the +1 bit signal DAT + can be made exactly in proportion
to the set value of the volume control signal VOLCTL.
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[0040]
In this manner, an error in the pulse width of the output 1-bit signal DAT +, DAT- can be
guaranteed with the accuracy of the system clock CK, that is, the accuracy of the crystal oscillator
with respect to the input 1-bit signal DAT. And when the clock frequency is 16 fs, control can be
performed in about 6%, and when it is 32 fs, control can be performed in about 3% of small
steps.
Further, the volume control signal VOLCTL corresponding to the reference voltage described
above is a binary signal. Therefore, the determination threshold does not change with respect to
fluctuations of the power supply voltage, etc., thereby realizing stable operation. Noise
generation can be prevented.
[0041]
The second embodiment of the present invention is described below with reference to FIG.
[0042]
FIG. 4 is a block diagram showing an electrical configuration of a peak value control circuit 21
which is a sound volume control apparatus according to a second embodiment of the present
invention.
The peak value control circuit 21 schematically shows a known power amplification circuit or the
like.
The peak value control circuit 21 is configured to include an amplifier 22, an input grinding
resistance Ri, and a feedback grinding resistance Rf.
The peak value control circuit 21 multiplies the input 1-bit signal DAT by Rf / Ri and outputs the
result as an output 1-bit signal DAT '.
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The feedback resistor Rf is a variable resistor, and by changing its resistance value, the gain of
the amplifier 22 is changed, and it is possible to obtain a 1-bit signal DAT 'of a desired peak
value. By passing this 1-bit signal DAT 'through a low pass filter, it is possible to obtain a volumecontrolled analog audio signal.
[0043]
Also in this case, the volume control can be performed with high accuracy without generating
noise.
[0044]
It will be as follows if the 3rd form of implementation of this invention is demonstrated based on
FIG.
[0045]
FIG. 5 is a block diagram showing the electrical configuration of the volume control circuit 31
according to the third embodiment of the present invention.
The volume control circuit 31 is configured by cascading the pulse width control circuit 1 and
the peak value control circuit 21 described above.
The pulse width control circuit 1 can control the pulse width with high accuracy in the step
corresponding to the clock frequency as described above, for example, about 6% in the case of
16 fs. On the other hand, the peak value control circuit 21 can control the peak value
continuously and variably although the power amplification element in the amplifier 22 is used
in the unsaturated region.
[0046]
Therefore, it is possible to finely adjust the volume obtained by the peak value controlled +1 bit
signal DAT + 'and -1 bit signal DAT-' by using these circuits 1, 21 in tandem connection.
Therefore, even if the sound volume is the same, amplification can be performed with high power
efficiency by controlling the pulse width so that the power amplification element in the amplifier
22 can be used in a region as close to the saturation region as possible. become.
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[0047]
It will be as follows if the 4th form of implementation of this invention is demonstrated based on
FIG.
[0048]
FIG. 6 is a block diagram showing the electrical configuration of the volume control circuit 41
according to the fourth embodiment of the present invention.
In general, the volume control circuit 41 switches the 1-bit signal DAT obtained by delta sigma
modulation to the pseudo signal dat generated by the pseudo signal generation circuit 42 when
no sound is present, and the respective circuits 1, 21 , 31 as a 1-bit signal DAT.
[0049]
Therefore, the low level detection circuit 43 performs analog conversion by converting the
output 1-bit signal DAT +, DAT- or DAT 'with a low-order low-pass filter and performs silence
detection, or silence detection from the muting signal ON / OFF etc. When it is detected that the
noise level is a silent level, the switch 44 is switched from the 1-bit signal DAT side to the pseudo
signal generating circuit 42 side to output the pseudo signal dat as the 1-bit signal DAT.
[0050]
The pseudo signal dat is a bit string in which “0” and “1” are alternately repeated.
As a result, a portion where "1" or "0" continues is generated due to quantization noise or the like
to the 1-bit signal DAT which should be a bit string in which "0" and "1" are alternately repeated
during silence. Even in this case, the 1-bit signal DAT actually input to each of the circuits 1, 21
and 31 can be a signal at the time of silence, and noise due to the quantization noise is generated
in the demodulated analog audio signal. It can be prevented.
[0051]
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The volume control circuit 41 outputs the output of the pulse width control circuit 1 or the
output of the peak value control circuit 21 as the +1 bit signal DAT + and the −1 bit signal DAT
− for the differential input amplifier in the subsequent stage. The pseudo signal dat, that is, the
output 1-bit signals DAT + and DAT−, is provided as a continuous bit string of only “0” when
it is provided in the subsequent stage of the mutually parallel buffers and inverters.
Also in this case, the same effect can be obtained.
[0052]
Although the present invention assumes that the 1-bit signal DAT is an audio signal, the present
invention can be widely implemented for power control of the 1-bit signal even if it is not an
audio signal.
[0053]
As described above, according to the first aspect of the present invention, the volume control
method for a 1-bit digital signal is synchronized with the 1-bit digital signal and uses the clock
signal having a sufficiently high frequency to perform the control. Control the pulse width of
[0054]
Therefore, the error of the pulse width can be guaranteed with the accuracy of the crystal
oscillator which is the clock signal source, and the volume control can be performed in minute
steps such as 6% and 3% corresponding to the clock frequency.
Furthermore, the determination threshold of the pulse width is determined by the count value of
the clock pulse, so that threshold fluctuation does not occur, stable operation can be performed,
and noise does not occur.
[0055]
Further, as described above, in the volume control method of the 1-bit digital signal according to
the invention of claim 2, the maximum value of the pulse width is less than the sampling period
of the 1-bit digital signal.
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[0056]
Therefore, even if there is a continuous portion of "1" or "0" in the input 1-bit digital signal, the
+1 bit digital signal and the -1 bit digital signal that are output have a sampling period of the 1bit digital signal. Inside, because it always switches from "1" to "0", the error of the pulse width
due to the waveform rounding etc. which occur at the rise and fall of the pulse is equal in the
case where the same data continues and alternates alternately. It is possible to control the
volume with higher accuracy.
[0057]
Furthermore, in the volume control method of the 1-bit digital signal according to the invention
of claim 3, as described above, the volume control is performed by controlling the peak value of
the 1-bit digital signal.
[0058]
Therefore, stable volume control can be stably performed with a simple configuration such as a
variable gain amplifier.
[0059]
Further, as described above, in the method of controlling the volume of a 1-bit digital signal
according to the invention of claim 4, the volume control shown in claim 1 or 2 and the volume
control shown in claim 3 are continuously executed mutually. .
[0060]
Therefore, the method according to claim 1 or 2, wherein the volume can be discretely controlled
in predetermined steps determined by the clock frequency, and the method according to claim 3,
wherein the power element is to be used in the unsaturated region. And the volume control in a
minute step can be performed with high power efficiency.
[0061]
Furthermore, according to the volume control method of a 1-bit digital signal in accordance with
the invention of claim 5, as described above, the output + 1-bit digital signal and the −1-bit
digital signal are only “0” when silent or muting. It is a signal.
[0062]
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Therefore, even if the input 1-bit digital signal has continuous parts of “0” or “1” due to
quantization noise, the output + 1-bit digital signal and −1-bit digital signal are forced to be a
signal string of only 0. The quantization noise can be removed from the demodulated analog
speech signal as
[0063]
In the sound volume control method of the 1-bit digital signal according to the invention of claim
6, as described above, the input 1-bit digital signal is alternately repeated with "0" and "1" at the
time of silence or muting. It is a signal.
[0064]
Therefore, even if there is a continuous portion of "0" or "1" due to quantization noise in the 1-bit
digital signal of the input, the 1-bit digital signal actually input is forced to "0" and "1". The
quantization noise can be removed from the demodulated analog speech signal as a signal
sequence that alternately repeats "."
[0065]
Furthermore, as described above, in the volume control device for a 1-bit digital signal according
to the invention of claim 7, when the 1-bit digital signal is "1" and "0" by the first and second
counters. Each clock signal of sufficiently high frequency is counted, and pulses are output from
the first and second flip flops until the count value matches the value corresponding to the
desired volume setting value.
[0066]
Therefore, it is possible to control the volume at a minute step corresponding to the clock
frequency and assuring an error of the pulse width with high accuracy of the crystal oscillator.
Also, there is no undesirable fluctuation of the threshold for the determination of the pulse width,
stable operation can be realized, and generation of noise can be prevented.
[0067]
Further, as described above, in the volume control device for a 1-bit digital signal according to
the invention of claim 8, when all the upper bits are "1" as the value corresponding to the volume
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setting value, the least significant bit Set to "0".
[0068]
Therefore, an interval always occurs between adjacent pulses of the output 1-bit digital signal,
and the pulse width error due to waveform rounding is equalized between the case where the
same data continues and the case where the same data alternates. It is possible to control the
volume with higher accuracy.
[0069]
Furthermore, as described above, according to the sound volume control device of a 1-bit digital
signal according to the invention of claim 9, a gain variable amplifier which amplifies and
outputs a pulse of a 1-bit digital signal with a gain corresponding to a desired volume setting
value. Equipped with
[0070]
Therefore, stable and accurate volume control can be performed by the gain variable amplifier
with a simple configuration.
[0071]
Further, as described above, according to the invention of claim 10, the volume control apparatus
for a 1-bit digital signal according to the invention of claim 10 mutually corresponds to the
volume control apparatus according to claim 7 or 8 and the volume control apparatus according
to claim 9. Connect in cascade.
[0072]
Therefore, it is possible to control the sound volume at predetermined steps determined by the
clock frequency, and therefore discretely, and to use the structure of the power element in the
unsaturated region. The combination with the configuration shown by 9 makes it possible to
perform volume control in minute steps with high power efficiency.
[0073]
Brief description of the drawings
[0074]
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17
1 is a block diagram showing an electrical configuration of a pulse width control circuit which is
a sound volume control device of the first embodiment of the present invention.
[0075]
2 is a block diagram showing a specific configuration of a pulse width control signal generation
circuit in the pulse width control circuit shown in FIG.
[0076]
3 is a waveform diagram for explaining the operation of the pulse width control circuit shown in
FIG.
[0077]
<Figure 4> It is the block diagram which shows the electrical constitution of the wave high value
control circuit which is the sound volume control control equipment of form of 2nd form of
execution of this invention.
[0078]
5 is a block diagram showing an electrical configuration of a volume control circuit according to
a third embodiment of the present invention.
[0079]
FIG. 6 is a block diagram showing an electrical configuration of a volume control circuit
according to a fourth embodiment of the present invention.
[0080]
Explanation of sign
[0081]
1 pulse width control circuit (volume control device) 2 pulse width control signal generation
circuit 3 clock signal source 4 volume setting means 6 flip flop (first flip flop) 7 flip flop (second
flip flop) 11 counter 12 data comparison Circuit (comparator) 21 Peak value control circuit
(volume control device) 22 Amplifier 31 Volume control circuit (volume control device) 41
Volume control circuit (volume control device) 42 Pseudo signal generation circuit 43 Low level
detection circuit 44 Switch Rf Feedback resistor Ri input resistance
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