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JP2010142639

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DESCRIPTION JP2010142639
An improved technique for addressing transducers in a two-dimensional transducer array. A
system and method for addressing transducers (22) in a two-dimensional transducer array (20)
according to an embodiment of the present technique is disclosed. In one aspect of the present
technique, the transducers (22) are arranged in rows and columns, and the columns are coupled
to common transmit and receive circuits (37, 38), while the rows are row select circuits (28).
Combined with). In another embodiment, each transducer (22) alone is coupled to a dedicated
transmit circuit (37), and the columns are coupled to a common receive circuit (38). [Selected
figure] Figure 2
System and method for operating a two dimensional transducer array
[0001]
The present invention relates generally to two-dimensional transducer arrays. The present
invention specifically relates to techniques for addressing individual transducer elements within
a two dimensional transducer array.
[0002]
Medical ultrasound imaging systems transmit an acoustic wave into an object and form an image
by receiving and processing the reflected acoustic wave. Typically, a plurality of ultrasonic
transducers emit transmit waves and receive reflected waves. These scans are a series of
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measurements as the ultrasound is transmitted, when the system switches to receive mode after
a short time interval, and when the reflected ultrasound is received, beamformed and processed
for display. including.
[0003]
The transducer elements are typically individually driven by the input voltage waveform. By
implementing time delays and amplitude differences between input waveforms, ultrasound waves
are synthesized to form a net ultrasound wave that propagates along the preferred vector
direction and focuses at the selected site of interest. Individual transducer elements can be
controlled to generate. Similarly, the reflected waves received by the transducer may be
mathematically processed such that the net signal is indicative of sound waves reflected from a
single focused zone within the object. As in the transmit mode, this focused reception of
ultrasound energy is achieved by adding various time delays and gains to the signals received
from the transducer elements and summing the resulting waveforms.
[0004]
U.S. Patent No. 4371805 U.S. Patent No. 5329496 U.S. Patent No. 5622658 U.S. Patent No.
5690114 U.S. Patent No. 2817023 U.S. Patent No. 583 9442 U.S. Patent No. U.S. Pat. No.
6,384,516 U.S. Pat. No. 6,552,964 U.S. Pat. No. 6,865,140 U.S. Pat. No. 6,875,177 U.S. Pat. No.
7,257,051 U.S. Pat. U.S. Patent Application No. 20050237858 U.S. Patent Application No.
2007016026 EP 1768101
[0005]
The quality or resolution of the image produced by the ultrasound imaging system is in part a
function of the number of transducers in the array.
Thus, to achieve high image quality, it is desirable to have a large number of transducer
elements. In addition, each transducer in the transducer array is coupled to transmit and receive
circuitry via individual electrical connections. The technical problems and expense associated
with making a large number of electrical connections may limit the number of transducers that
can be included in a typical transducer array. Therefore, it would be advantageous to be able to
provide an improved technique for addressing transducers that are in a large two-dimensional
transducer array.
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[0006]
Disclosed are systems and methods for addressing transducers in a two-dimensional array
according to embodiments of the present technique. In one aspect of the present technique, the
transducers are arranged in rows and columns, the columns being coupled to a common transmit
and receive circuit while the rows are coupled to a row select circuit. In another embodiment,
each transducer is independently coupled to a dedicated transmit circuit, and its column is
coupled to a common receive circuit. In both of these embodiments, the number of individual
electrical interconnections used to communicatively couple the transducers to the signal
generation / reception circuitry is reduced.
[0007]
These features, aspects and advantages as well as other features, aspects and advantages of the
present invention can be read by the following detailed description with reference to the
accompanying drawings in which like reference numerals represent like parts throughout the
drawings. Will be better understood.
[0008]
FIG. 7 is a diagram of an exemplary ultrasound device including a two-dimensional transducer
array in accordance with the improved technique for addressing individual transducers in
accordance with aspects of the present invention.
FIG. 2 is a block diagram of the two-dimensional transducer array shown in FIG. 1 in accordance
with an aspect of the present invention. 5 is a graph of voltage versus time representing row
select timing and corresponding voltage output of the transducer array shown in FIG. 2 in
accordance with an aspect of the present invention. FIG. 4 is an expanded graph of voltage versus
time shown in FIG. 3 illustrating row select timing of the first three rows of transducers
according to aspects of the present invention. FIG. 5 depicts an alternative embodiment of a twodimensional transducer array according to aspects of the present invention. FIG. 7 depicts an
alternative embodiment of a receiver circuit for use in a transducer array in accordance with an
aspect of the present invention. FIG. 7 depicts an alternative embodiment of a receiver circuit for
use in a transducer array in accordance with an aspect of the present invention. FIG. 7 depicts an
alternative embodiment of a receiver circuit for use in a transducer array in accordance with an
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aspect of the present invention.
[0009]
The techniques disclosed herein allow for the fabrication of transducer arrays without the use of
separate dedicated processing electronics for each transducer. According to the embodiments
disclosed herein, two-dimensional transducer arrays can be fabricated that use multiple signal
buses so that each can be shared by several transducers. In order to enable activation of the
individual transducers, the transducers may be coupled to the signal bus through switches
activated by the selection circuit. By providing a less technical problem and more economical
technique for addressing transducers in the array, larger transducer arrays can be fabricated
compared to existing ultrasound technology This allows new ultrasound techniques and devices
with large two-dimensional transducer arrays.
[0010]
FIG. 1 is an exemplary ultrasound device including a two-dimensional transducer array in
accordance with the improved technique for addressing transducers in accordance with aspects
of the present invention. As shown in FIG. 1, the enhanced ultrasound device 10 may be
positioned adjacent to the tissue of the patient 12 and coupled to the monitor 14 through the
communication cable 16. The monitor 14 allows an operator of the ultrasound device 10 to
reconstruct and view an ultrasound image created from the signals received by the ultrasound
device 10. Further, the monitor 14 may provide control signals to the ultrasound device 10
through the communication cable 16. The ultrasound device 10 may include a housing 18 that
serves to encompass the transducer array 20 and allow the transducer array 20 to be in close
proximity to the tissue of the patient 12. The housing 18 may include a thin, flexible material
that allows the ultrasound device 10 to be aligned with the tissue of the patient 12. In some
embodiments, the housing may include, for example, an elastomeric polymer such as a silicon
based polymer, polyvinyl chloride, or a polyolefin such as polyethylene. The housing 18 may
further include an adhesive backing to hold the ultrasound device 10 in place. Alternatively, the
ultrasound device 10 may be held in place by elastic bands or straps.
[0011]
The transducer array 20 is disposed within the housing 18 and is held in close proximity to the
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patient 12 by the housing 18. The transducer array 20 may be further flexible to provide good
contact with the tissue of the patient 12. In one embodiment, the transducer array 20 may
generally be up to 6 "high and 6" wide, and may be up to about 1,000,000 transducers arranged
in a 1000 x 1000 matrix. May be included. This large number of transducers enables an
automatic scan such that the operator does not move the ultrasound device 10 to acquire
ultrasound images across several image slices within the site of interest. Otherwise, several image
slices may be obtained by scanning the rows of the transducer array 20 electronically. In order to
reduce the number of electrical interconnections used within transducer array 20, transducers
may be coupled to several signal buses or common interconnections (this will be described
below).
[0012]
FIG. 2 is a block diagram of the large two-dimensional transducer array 20 shown in FIG. 1 in
accordance with an aspect of the present invention. Transducer array 20 includes transducers 22
arranged in a grid. For convenience, only two rows and two columns of transducer array 20 are
shown. However, it should be understood that the transducer array according to this embodiment
may include the number of rows and the number of columns such that the total number may be
up to several million transducers 22. Transducer 22 can be any type of ultrasound transducer,
such as, for example, a capacitive micromachined ultrasound transducer (cMUTS) or a
piezoelectric transducer.
[0013]
Each of the transducers 22 in a single column electrically interconnects each of the transducers
22 in the column to circuitry configured to transmit and receive ultrasound signals to the
transducers 22. It may be coupled to the column bus 24. Each transducer 22 may be selectively
coupled to the column bus 24 through a switch 26. The switch 26 can be any type of solid state
or other suitable switch such as a field effect transistor or micro-electromechanical system
(MEMS) switch, and can be high to support the transmission voltage. May allow the passage of
voltage (50-200 V). The gate of each switch 26 may be coupled to a row bus 25 which is an
electrical connection coupling each row of transducers to a row selection circuit 28. Row select
circuit 28 selectively activates one or more rows of transducers 22 by transmitting signals to the
gates via row bus 25, thereby coupling selected rows of transducers 22 to column bus 24. There
is something I can do. The transducers 22 can be addressed individually or one or more rows at a
time by controlling the signals that are placed on the column and row buses.
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[0014]
A column bus 24 couples each column of transducers 22 to a transmitter circuit 37 and a
receiver circuit 38 through a transmitter / receiver (T / R) switch 34, which transmits the column
bus 24 to transmitter circuit 37. It is determined which of the two is to be coupled to the
reception circuit 38. The transmitter circuit 37 may include control logic 30 configured to
control the generation of the output voltage waveform that is sent to the transducer 22 via the
column bus 24. Control logic 30 may send one or more control signals to pulse generator 36 to
generate an output voltage waveform, the output of which is coupled to column bus 24 and
predefined. Are configured to output a plurality of discrete voltage levels. A signal from control
logic 30 steps the output voltage of pulse generator 36 along a predefined voltage level to
produce the desired output voltage waveform. In some embodiments, the pulse generator 36
may generate a square wave with three voltage levels: 0, + V and -V. In another embodiment, the
pulse generator 36 may output a waveform that includes several voltage levels and resembles a
sinusoidal waveform. In yet another embodiment, the pulse generator 36 may generate an analog
output waveform. Additionally, control logic 30 and / or pulse generator 36 may be configured
to generate different waveforms for each column bus 24. For example, in some embodiments, the
control logic 30 may generate a phase delay between the output waveforms of each column bus
24 such that the entire ultrasound is focused to a particular site of interest.
[0015]
Reception circuitry 38 may include data acquisition circuitry 32 that receives data representing
from the transducer 22 data representing ultrasound reflected from the patient 12. Data
acquisition circuitry 32 may then create an ultrasound image from this data. Data acquisition
circuitry 32 may further introduce phase delays and signal gain deviations to the received data to
focus the ultrasound image on a particular site of interest in the patient. The receiver circuit 38
may further include circuitry for converting the voltage waveform received from the transducer
into digital form suitable for the data acquisition circuit 32. In some embodiments, the receiver
circuit 38 may include an amplifier 40 and an analog to digital converter (ADC) 42. Amplifier 40
may receive a voltage signal from transducer 22 and may amplify this signal to a level suitable
for ADC 42. The ADC 42 then converts the signal received from the transducer 22 into a digital
signal, which may be sent to the data acquisition circuit 32 for processing.
[0016]
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The T / R switch 34 controls routing of signals to the column bus by controlling which of the
transmission circuit 37 and the reception circuit 38 the column bus 24 is coupled to. During the
transmit phase, the T / R switch 34 couples the output signal from the pulse generator 36 to the
column bus 24 so that the output signal is transmitted to the row of transducers 22 selected by
the row selection circuit 28. During the receive phase, T / R switch 34 couples column bus 24 to
amplifier 40. The signal that amplifier 40 receives from transducer 22 is then digitized by ADC
40 before being relayed to data acquisition circuit 32.
[0017]
By using the addressing techniques described above, it is possible to selectively activate the
individual transducers 22 without using the individual interconnections for each transducer 22.
For example, in a 100 × 100 transducer array, the number of interconnections can be reduced
from 10,000 to 200. This can result in significant savings in fabrication costs as compared to
typical ultrasound devices, and allows the fabrication of even larger transducer arrays. In some
embodiments, the ultrasound device may be configured to simultaneously address the entire
transducer array 20, or desired subsets of the transducer array 20, such as individual rows and
columns.
[0018]
The process of acquiring ultrasound data may include two stages, an output stage and a
reception stage. During the output phase, the T / R switch 34 couples one or more of the column
buses 24 to the output of the pulse generator 36 and the control logic 30 then sends it to the
column bus 24. An output waveform is generated. The row select circuit 28 then activates one or
several of the switches 26 so that the selected transducer 22 is coupled to the column bus 24.
The selected transducer 22 then receives the output voltage waveform from the pulse generator
36 and transmits the resulting ultrasound waveform to the patient 12. As discussed further
below in conjunction with FIG. 3, in some embodiments, the row select circuit 28 sequentially
activates each row of transducers 22 for a short period of time while generating the output
waveform. May cause the entire array 20 to be scanned.
[0019]
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During the receive phase, the T / R switch 34 couples one or more of the serial buses 24 to the
input of the receive circuit 38. The row select circuit then activates one or several of the switches
26 so that the selected transducer 22 is coupled to the column bus 24. The selected transducer
22 then receives the ultrasound waveform reflected from the patient 12 and sends the resulting
electrical signal to the receiving circuit 38 where it is digitized and processed to create an
ultrasound image. As in the transmit phase, the row select circuit 28 scans the entire array 20 by
sequentially activating each row of transducers 22 for a short period of time while receiving the
reflected ultrasound waveform. May be configured. Row select timing may be better understood
with reference to FIGS. 3 and 4 which illustrate an exemplary method of addressing a transducer.
[0020]
FIG. 3 is a graph of voltage versus time representing row select timing and corresponding voltage
output of the transducer array shown in FIG. 2 in accordance with an aspect of the present
invention. For the purposes of this illustration, a 100 × 100 matrix ultrasound transducer is
assumed. Included within the graph 46 is a plot of the column bus output 48 generated by one of
the pulse generators 36 shown in FIG. As shown in FIG. 3, the column bus output 48 rises from
zero volts at time zero to a positive voltage Vpos which is a quarter of an output period 56
(Tout). In some embodiments, Vpos may be approximately equal to 100 volts. Thus, it should be
understood that in some embodiments, the switch 26 shown in FIG. 2 will be a high voltage
switch. The column bus output 48 is a stepped output approximating a sinusoidal waveform. In
alternative embodiments, the column bus output 48 may be an analog signal or a square wave
signal. Further, it should be noted that graph 46 shows only one quarter of the serial bus output
48 for convenience. In the illustrated exemplary embodiment, the output frequency of the
cascade bus signal may be approximately 5 megahertz. Thus, in the illustrated embodiment, the
output period of the column bus signal is approximately 200 nanoseconds, and the quarter
period 56 (ie, the time for raising the column bus output 48 from zero to Vpos) is approximately
50 nanoseconds. There is.
[0021]
As discussed above, the rows of transducer array 20 may be scanned or activated sequentially
while outputting the column bus signal 48. Each time a row is activated, it remains active for a
period of time (referred to herein as a "row activation interval"), during which time the
transducers in the activated row are activated. Electrically charge or discharge according to the
bus voltage. Cycle time 58 (Tcycle) refers to the amount of time it takes to scan the entire
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transducer array 20. In some embodiments, the entire transducer array 20 may be scanned every
10 nanoseconds, in which case the 100 row transducer array 22 has a row activation interval of
0.1 nanoseconds. As shown in FIG. 3, in some embodiments, the transducer array 20 may receive
several scans while outputting the column bus signal 48. Thus, as the column bus voltage
changes in response to the output voltage waveform from pulse generator 36, transducer 22
may be activated several times. Each time the transducer 22 is activated, it charges or discharges
according to the column bus voltage present during the activation interval. Because the
transducer is capacitive, the high frequency components introduced by the switching of the row
selection circuit 28 are filtered out by the transducer 22 so that the output ultrasound waveform
of the transducer 22 approaches a smooth waveform.
[0022]
The graph 46 shows the voltages applied to the transducers 22 of Row 1 and Row 50 when
sequentially activating 100 rows. Trace 50 represents the voltage applied to row 1 and trace 52
represents the voltage applied to row 50. As shown in graph 46, row 1 is switched on shortly
after time zero, by which time column bus signal 48 has been stepped up to the initial voltage
level. While row 1 remains activated, transducers 22 of row 1 are charged until the voltage level
of column bus 24 is reached. Since all 100 rows are activated during cycle time 58, each row is
activated for a time period equal to or less than the cycle time divided by the number of rows (in
this case Tcycle / 100) There is. However, after the transducer 22 is switched off, the output of
the transducer 22 is maintained at the final voltage level reached during the start-up period.
After one cycle time 58 (Tcycle), Row 1 is switched on again, and Row 1 reaches the voltage level
present on the column bus at that time. This process continues until transmission of the output
waveform is complete for each row of transducers 22. It will be important to point out that
although each transducer row is activated at slightly different times during the scan cycle, the
phase difference between the output waveforms of the different rows is very small. This may be
better understood with reference to the row 50 shown by trace 52.
[0023]
As shown by the graph 46, the row 50 is activated at time Tcycle / 2 and is activated again after
each successive time interval Tcycle. As can be seen from this graph, row 1 and row 50 are
switched on at different times, but since both of these two waveforms are sampling the output
voltage waveform, there is a phase delay present between these two waveforms Is very small.
However, it should be understood that a slight amount of phase delay may be introduced by the
column bus signal 48 depending on the switching interval 54 between transducer rows. In
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general, the phase delay between transducer output waveforms is less than or equal to the
switching interval 54 of the column bus (Tbus).
[0024]
FIG. 4 is an enlarged view of the graph shown in FIG. 3 depicting the row selection timing of the
first three rows of transducers according to aspects of the present invention. FIG. 4 represents
the voltage across transducer 22 immediately after time zero while Row 1, Row 2 and Row 3 are
selected. As shown in FIG. 4, column bus signal 48 rises to a first voltage increment V1 shortly
after time zero. Subsequently, row 1 represented by trace 50, row 2 represented by trace 62, and
row 3 represented by trace 64 are switched on successively. As mentioned above, the
embodiments described herein assume a transducer array 20 with 100 rows and a 10
nanosecond cycle time 58 (Tcycle). Thus, the row activation interval 59 of the embodiment
described herein is approximately 0.1 nanoseconds. In other words, the row selection circuit 28
sequentially activates successive transducer rows in 0.1 nanosecond increments. Thus, as shown
in graph 60, row 1 is switched on at T = 0.1 nanoseconds. At T = 0.2 nanoseconds, row 1 is
switched off and row 2 is switched on. At T = 0.3 nanoseconds, row 2 is switched off, row 3 is
switched on, and so on. In some embodiments, the rise time 66 (Trise) of the column bus signal
48 may be shorter than the row activation interval 59, such that the column bus signal 48 has
each incremental voltage level (on) before the transducer row is switched on. For example, the
voltage V1) can be stabilized.
[0025]
The same process of sequentially selecting the individual rows may be implemented during the
receive phase, with the reflected ultrasound waveform being received by the transducer 22 and
the transducer 22 receiving circuitry 38 via the column bus 24. Generate a corresponding
voltage signal to be delivered to the To avoid aliasing, the sampling rate of transducer 22 may
exceed twice the frequency of the received ultrasound waveform. Thus, for a 5 megahertz
ultrasonic waveform, the sampling rate of the transducer 22 may be in excess of approximately
10 megasamples per second (MSPS). Thus, for a 100 row transducer array 20, the switching
frequency of the row selection circuit is approximately one gigasample per second (GSPS).
Furthermore, since each column of transducers shares the same ADC 42, the sample rate of the
ADC 42 will also be approximately 1 GSPS.
[0026]
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FIG. 5 depicts an alternative embodiment of a large two-dimensional transducer array according
to aspects of the present invention. In the embodiment shown in FIG. 5, each transducer 22 in
the array 20 is associated with a dedicated transmit pulse generator 36. Rather than collecting
transmit signals from the column bus 24, each dedicated pulse generator 36 provides an output
voltage waveform to the associated transducer 22 in response to the drive signal from the
associated control logic 30. Control logic 30 may be programmed to generate a full output
waveform in response to a synchronization signal from transmit synchronization circuit 27 that
may be communicatively coupled to control logic 30 via global control line 23. In this
embodiment, a synchronization signal from transmit synchronization circuit 27 may trigger
control logic 30 simultaneously, causing transducer 22 to simultaneously transmit output
waveforms. Furthermore, customizing the control logic 30 and / or the pulse generator 36 for
each drive unit may make the waveforms of each transducer 22 more individual.
[0027]
In an alternative embodiment, the transmit synchronization circuit 27 may be eliminated. In this
embodiment, the start of the output ultrasound waveform will be governed by sending a
synchronization signal to the control logic 30 through the row bus 25 by the row select circuit
28. As with the illustrated embodiment, synchronization signals may be sent sequentially or
substantially simultaneously to all rows. Control logic 30 may then initiate a routine that drives
pulse generator 36 to generate an output waveform.
[0028]
The output of each transducer 22 may be coupled to the column bus 24 to route the output
signal from the transducer 22 to the receiving circuit 38. Further, each transducer 22 may be
coupled to the column bus 24 through a T / R switch 34 that controls the routing of signals into
and out of the transducer 22 and / or through a switch 26 that controls the selection of
transducer rows. In addition to driving the pulse generator 36, the control logic 30 may also
control the T / R switch 34. For example, during the transmit phase, control logic 30 may send a
signal that couples transducer 22 to the output of pulse generator 36 for the T / R switch.
Because the transmission resources are not common, all of the transducers 34 may also be
simultaneously coupled to the respective pulse generators 36 during the transmission phase.
During the receive phase, control logic 30 may signal T / R switch 34 to couple transducer 22 to
column bus 24. Depending on the startup speed of the T / R switch 34, a low voltage MOSFET
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row select switch may be used instead. During the receive phase, only one of the rows of
transducers 22 may be coupled to the column bus 24 at one time. Thus, row select circuit 28
may sequentially couple transducers 22 to column bus 24 one row at a time while receiving the
reflected ultrasound waveform. As described above in connection with FIG. 3, the output of the
transducer 22 may be sent to a receiver circuit 38 which may include an amplifier 40 and an
ADC 42.
[0029]
As shown in FIGS. 2 and 5, the receiver circuit 38 will be common to each column bus 24 in
some embodiments, and the receiver circuit 38 is shared by the transducers 22 coupled to the
column bus 24. It will be. Thus, as noted above, the sampling rate of receiver circuit 38 may be
the sampling rate of transducer 22 multiplied by the number of rows in transducer array 20.
Assuming a transducer sampling rate of 10 MSPS and a row of transducers 22 of 100, the
sampling rate of ADC 42 may be approximately 1 GSPS. Furthermore, the data received by data
acquisition circuitry 32 may be interlaced across several rows. However, in another embodiment,
the receive circuitry 38 may be arranged to enable utilization of the ADC 42 with reduced
processing speed and to provide some kind of pre-processing on the received sample data. For
example, the receive circuitry 38 shown in FIGS. 6 and 7 represents an alternative embodiment
of the receive circuitry 38 that can temporarily store sample data in an analog memory device as
it is received from the transducer array 20. In this manner, the processing speed of the ADC (s)
may be reduced and / or the data may be pre-processed before being sent to the data acquisition
circuit 32 (for this further below) To explain).
[0030]
FIG. 6 depicts an alternative embodiment of receiver circuit 38 in accordance with aspects of the
present invention. As shown in FIG. 6, the receiver circuit 38 may include an array 74 of analog
storage devices such as sample and hold (S / H) amplifiers 76 and ADCs 42. In some
embodiments, the analog storage device may include analog random access memory (RAM).
Array 74 may include a pairing of one S / H amplifier 76 and one ADC 42 for each transducer 22
in transducer array 20. To this end, the S / H array 74 may be arranged in rows and columns in
alignment with the respective rows and columns of the transducer array 20. Each S / H amplifier
76 may receive waveform data reflected from one of the transducers 22 of the transducer array
20 via the column bus 24. For example, S / H amplifiers 76 in column 1 of array 74 receive data
from transducers 22 in column 1 of transducer array 20, and S / H amplifiers 76 in column 2 of
array 74 are columns of transducer array 20. Data is received from transducer 22 in 2, and so
04-05-2019
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on. S / H amplifiers 76 may be coupled to their respective column buses 24 by any suitable
means. For example, column bus 24 may be multiplexed into a particular column of S / H
amplifiers 76. In another example, the column bus 24 may be fed into a pipeline, such as a
charge coupled device (CCD). In yet another example, a particular column of S / H amplifiers 76
may be arranged in series and coupled via a shift register, and column bus 24 may be coupled to
the input of the shift register column There is.
[0031]
During the receive phase, the column bus 24 of the transducer array 20 is coupled to a particular
row of transducers 22 in the transducer array 20 and the received data samples are stored in
corresponding rows of the S / H amplifier 76. Be done. After the rows of S / H amplifiers 76 have
newly collected data samples, each S / H amplifier 76 sends the data samples to the associated
ADC 42 to convert the analog data to digital signals. The digitized samples are then sent to data
acquisition circuit 32 via data line 44. The above-described processing is sequentially performed
in row units. It should be appreciated that there may be one data line 44 from the S / H array 74
to the data acquisition circuit 32 for each transducer 22 in the transducer array 20. Furthermore,
the processing speed of the ADC 42 may be equal to the sample speed of the transducer 22 since
each S / H amplifier 76 is paired with a single ADC 42. For example, assuming that the
transducer sampling rate is 10 MSPS, the processing speed of the ADC 42 may also be
approximately 10 MSPS, regardless of the number of rows of transducers 22.
[0032]
FIG. 7 depicts another embodiment of receiver circuitry 38 in accordance with an aspect of the
present invention. Similar to the embodiment shown in FIG. 6, the embodiment shown in FIG. 7 is
also a sample and hold (S / H) amplifier arranged in rows and columns corresponding to each
row and column of the transducer array 20. An array 74 may be included, and each S / H
amplifier 76 may receive waveform data reflected from one of the transducers 22 of the
transducer array 20 via the column bus 24. However, in the embodiment shown in FIG. 7, each
row of S / H amplifiers 76 is paired with one ADC 42.
[0033]
In this embodiment, after the rows of transducers 76 receive data samples, the rows of S / H
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amplifiers 76 are read out sequentially to the ADC 42. Each row of S / H amplifiers 76 may be
coupled to a respective ADC 42 by any suitable means. For example, rows of S / H amplifiers 76
may be multiplexed into ADC 42. In another example, a row of S / H amplifiers 76 may form a
pipeline, such as a CCD pipeline. In yet another example, the rows of S / H amplifiers 76 may be
arranged in series and coupled together via a shift register. In this manner, the number of data
lines 44 from the S / H amplifier array 74 to the data acquisition circuit 32 can be reduced.
Furthermore, it should also be understood that sample data collected in this manner may be
rearranged from the interlace column to the interlace row before being sent to the data
acquisition circuit.
[0034]
FIG. 8 depicts yet another embodiment of receiver circuitry 38 in accordance with aspects of the
present invention. In the illustrated embodiment, each column bus 24 of transducer array 20 is
coupled to an analog RAM bank 80 that includes one analog RAM 82 for each transducer 22 in
transducer array 20. Each RAM 82 includes a series of contiguous memory addresses configured
to store the reflected waveform data received by the corresponding transducers 22 in the
transducer array 20. As the rows of transducer array 20 are sequentially activated by row
selection circuit 28 during the receive phase, data from transducers 22 may be saved in
corresponding RAM 82. Thus, each RAM bank 80 may include circuitry for coupling each row in
transducer array 20 to a corresponding RAM 82 in RAM bank 80. For example, in some
embodiments, the RAM bank 80 may include multiplexing circuitry that sequentially couples the
column bus 24 to the appropriate RAM 82, and may be coordinated with the activation of the
rows of the transducer array 20 by the row selection circuit 28. In some embodiments, the
multiplexing circuitry of RAM bank 82 may be controlled in part by row selection circuitry 28.
After reception of the reflected waveform is complete, the reflected waveform for each
transducer 22 will be saved in the individual RAM 82. This waveform is then read from the RAM
82 and sent to the data acquisition circuit 32 (this will be described below).
[0035]
In some embodiments, the receiver circuit 38 may include an adder 86 that sums the reflected
waveforms one row at a time as they are read from the analog RAM bank 80. For example, RAM
bank 80 reads the first memory address of each RAM 82 within a single row of RAM bank 80,
and then reads the second memory address of each RAM 82 within the same row of RAM bank
80, and so forth. The same may be done until the entire set of data in the row in question is read
out and added up. As the data is summed, the output of summer 86 is sent to ADC 42, which
04-05-2019
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digitizes the data and sends it to data acquisition circuit 32. The data sent to data acquisition
circuitry 32 is thus a composite waveform that represents the entire row of transducers 22. Each
row is summed continuously until all data from each analog RAM bank 80 has been read.
According to the technique described with reference to FIG. 8, reducing the sample rate of the
ADC 42, as processing of the output data may be performed after receipt of the full reflection
waveform, and thus is independent of the sample rate of the transducer 22. Is possible. Further,
by combining the outputs of each column into a summation signal, only one ADC 42 is used, and
the data acquisition circuit 32 only includes one input for receiving reflection data. This may
reduce the cost and complexity of the receiver circuit 38 and the data acquisition circuit 32.
[0036]
Another advantage of the receiving circuit 38 shown in FIG. 8 is the process that allows the
ultrasound beam to be targeted in a particular direction, ie a process that can increase the
sensitivity of the ultrasound device 10 in a particular direction. It can also be used to realize
beamforming. To achieve such beamforming, two or more of the reflected waveforms are shifted
(i.e., time shifted) to be in phase and summed with one another to represent a wave reflected
from a particular direction Can be generated. The receiver circuit 38 of FIG. 8 may introduce a
time delay to the data by shifting the data stored in each RAM 82 across one or more memory
addresses. In this method, as data is read out sequentially from RAM 82, this shift of data causes
the data to be sent to the adder with a time delay relative to the other waveforms. Thus, the time
delay introduced by the data shift will depend on the sample rate of the transducer 22 as well as
the number of the memory address that shifts the data.
[0037]
In one embodiment, the data shift is accomplished by setting the starting memory address as
indicated by the pointer 84. The pointer 84 determines where in the analog RAM 82 the first
data sample of the reflected waveform is stored. Thus, the analog RAM 82 may include sufficient
memory to hold the full reflection waveform plus the maximum time delay. After all the output
data from the transducer 22 is stored in the analog RAM 82, the desired delay is realized. When
the reflected waveform data is subsequently read out from each RAM 82, the reading is started at
the first memory address of each RAM 82.
[0038]
04-05-2019
15
Technical effects of the invention include that one or more transducers in the transducer array
are addressed to generate ultrasound and / or receive reflected ultrasound, wherein The
transducers are to be coupled to a common electrical interconnect. Another technical effect
includes preprocessing of the received ultrasound data to allow reduction in processing speed for
analog to digital converters and data acquisition circuits.
[0039]
This description is to disclose the invention (including the best mode) and to enable the practice
of the invention including the fabrication and use of any device or system and any method
incorporated by those skilled in the art. I'm using an example. The patentable scope of the
invention is defined by the claims, and may include other examples that occur to those skilled in
the art. Such other examples may have structural elements that do not differ from the character
representations of the claims, or may have equivalent structural elements that do not differ
substantially from the character representations of the claims. , Intended to be within the scope
of the claims.
[0040]
Reference Signs List 10 ultrasonic device 12 patient 14 monitor 16 cable 18 housing 20
transducer array 22 transducer 23 control line 24 column bus 25 row bus 26 switch 27
transmission synchronization circuit 28 row selection circuit 30 control logic 32 data acquisition
circuit 34 transmission / reception switch 36 pulse Generator 37 transmitter circuit 38 receiver
circuit 40 amplifier 42 ADC 44 data line 46 graph 48 column bus output 50 trace 52 trace 54
switching interval 56 output cycle 58 cycle time 59 row start interval 60 graph 62 trace 64 trace
66 rise time 74 analog storage Array of Devices 76 Sample and Hold Amplifiers 80 RAM Bank 82
RAM 84 Pointer 86 Adder
04-05-2019
16
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