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A large area modular sensor array assembly is formed. A modular, tileable sensor array (101)
having routing within the interposer that conveys signals from the sensor to the integrated
circuit (106). The large area modular sensor array assembly includes one or more tileable
modules coupled together. The tileable module comprises a plurality of transducer cells (103)
forming a sensor, an interposer coupled onto the first side of the plurality of transducer cells, and
one or more coupled to the second side of the interposer And the interposer is configured to
form a connection to the integrated circuit of the plurality of transducer cells. [Selected figure]
Figure 1
Large area modular sensor array assembly and method of making same
Ultrasonic monitoring and imaging systems use a transducer array to generate short high
frequency acoustic pulses that are reflected from interfaces where there is a change in acoustic
impedance. The transducers convert the reflected energy into electrical signals, which are
processed to generate two-dimensional or three-dimensional image information depicting the
object of investigation.
There are several applications where large area "patch" -type ultrasound transducer arrays can
be used, such as cancer screening and continuous non-invasive blood pressure monitoring. The
number of elements in large area transducers can vary from 10,000 to over 1,000,000
depending on the application. Considering the large number of transducer elements, each having
its own signal processing circuit, there is considerable power, cost and area loss.
One way to reduce the number of signal processing channels for such a large area array is to use
a mosaic annular reconfigurable array. Capacitive micromachined ultrasonic transducers
(cMUTs), which are micro-electro-mechanical system (MEMS) structures, are also alternatives to
conventional PZT-based ultrasonic transducers.
For ultrasound probe applications, the transducer array of the ultrasound probe assembly
generally covers an area of about 10 cm <2>. For new medical applications such as internal
bleeding and testing for tumors, much larger arrays of as much as 1000 cm <2> are required. For
non-medical applications, larger arrays are desired.
Such large arrays can be formed by tiling a number of transducer modules, each comprising a
sub-array of transducer cells and an integrated circuit coupled to the sub-array. However, when
there are significant gaps or variations in spacing between modules, the performance of the large
transducer area is significantly degraded.
A mosaic array configuration generally groups together multiple subelements along equal phase
lines to form larger transducer elements, which are then each connected to one system channel.
In this way, an array with tens of thousands of active acoustic subelements can be reduced to a
very small number (e.g. 20 to 100) of system processing channels. This greatly reduces the
system requirements and enables a low power, low complexity electronic component system for
large area arrays. In order to realize such an array configuration, switching electronics are
generally integrated directly behind the acoustic array. These switching circuits implemented
using dedicated ASICs are connected directly to the respective subelements and can be
programmed to short them together in a reconfigurable manner. One of the main challenges with
such systems is the interconnection of many transducers with their respective switching circuits
on adjacent ASICs.
An acoustic transducer cell is generally a multilayer structure comprising a piezoelectric
transducer or micromachined transducer configured with electronic circuitry in a probe
assembly. The electrical signals are further processed by beam forming circuitry, generally
external to the probe assembly, to generate and display an image of the structure being
For ultrasound probes, it is desirable to include a portion of the beam forming circuitry
integrated into the transducer array. This is because it can reduce complexity and, in some cases,
reduce the adverse effects caused by the connecting cable between the transducer probe and the
external system providing the signal processing and control function. . For example, if the
connecting cable extends over a distance of several meters, significant capacitive effects may
occur. In addition, signals received from the transducer assembly may be weak, susceptible to RF
interference, and exhibit an undesirably low signal to noise (S / N) ratio. To mitigate these effects,
front end circuit cells providing, for example, amplification, pulse generation, and transmit /
receive switching can be integrated with the transducer array.
In the prior art, sensor / ASIC assemblies are generally not capable of tiling and modularization.
Arrays of such assemblies are assembled using, for example, flexible based interconnects or wire
bonds. Stacked assemblies are assembled using multiple component interposers and flip chip
bonding. However, there are benefits to the structure and processing of the transducer array that
mitigates the problems encountered with existing designs.
U.S. Patent No. 7375420
One embodiment of the present system is a large area modular sensor array assembly having at
least one tileable module.
The tileable module comprises a plurality of transducer cells forming at least one sensor, an
organic interposer having a first surface bonded to the plurality of transducer cells, and one or
more bonded to a second surface of the interposer. A plurality of integrated circuits, the
interposer includes a plurality of electrical interconnections to at least some of the transducer
cells and to at least some of the integrated circuits. There is at least one input / output connector
having a length extending substantially perpendicular to the interposer and providing an external
interface, the length of the input / output connector being greater than the thickness of the
integrated circuit. The substrate is coupled to the tileable module and electrically coupled to the
input / output connector.
One method of forming a large area modular sensor array assembly includes providing a
motherboard and coupling one or more tileable modules to the motherboard. The tileable module
comprises the steps of bonding the plurality of transducer cells to the first side of the interposer
by the plurality of first side bumps and at least the second side of the interposer by the plurality
of second side bumps. Connecting the integrated circuit to one integrated circuit, coupling the
transducer cells to the integrated circuit by providing the interposer with a plurality of electrical
interconnections, and forming the input / output connection on the interposer, the input / output
connection Is longer than the thickness of the integrated circuit, thereby providing an electrical
connection to the motherboard.
A further embodiment includes a transducer sensor array having a plurality of transducer cells,
some of which form at least one grooved sensor. There are one or more integrated circuits, each
integrated circuit having a defined thickness. The organic interposer is sandwiched between the
transducer cell and the integrated circuit, the transducer cell is bonded to a first side of the
interposer, and the integrated circuit is bonded to a second side of the interposer. The interposer
includes a plurality of electrical interconnections between at least some of the transducer cells
and at least some of the integrated circuits. There is at least one input / output connector joined
on the same side of the interposer as the integrated circuit and having a length greater than the
defined thickness of the integrated circuit. The input / output connector is electrically coupled to
at least one of the transducer cells or the integrated circuit, and there is a substrate electrically
coupled to the input / output connector having an electrical connection from the substrate to an
external resource.
The present invention will be more clearly understood from the following description in which
one or more embodiments are given by way of example only, with reference to the accompanying
drawings, and like reference numerals indicate like features throughout the drawings. Used in
Individual features in the drawings may not be to scale.
FIG. 1 is a general block diagram of an ultrasound imaging system. FIG. 5 is a partial plan view of
an array transducer assembly according to one embodiment. FIG. 1 is a cross-sectional view of a
flip chip array transducer assembly according to one embodiment. FIG. 5 is a flow chart of a flip
chip array transducer assembly according to one embodiment. FIG. 7 is a cross-sectional view of
another example of a transducer assembly showing electrical interconnections according to one
embodiment. FIG. 5 is a perspective view of the top of a large modular transducer array having a
scanning aperture according to one embodiment. Figures 7a and 7b are perspective views
showing the tiling possible module configuration of the transducer according to the invention.
FIG. 5 is a cross-sectional view of an example of a mounted transducer module according to one
embodiment. FIG. 7 is a cross-sectional view of a further example of a mounted transducer
module according to one embodiment. FIG. 7 is a cross-sectional view of another example of a
mounted transducer module according to one embodiment. 11a and 11b are cross-sectional
views illustrating the spacing between the die and the module of the transducer module
according to one embodiment. FIG. 16 is a real image showing a mechanical cMUT flip chip
attached to the top of the interposer. FIG. 1 illustrates a test system according to one
embodiment. 5 is a flow diagram for a large area sensor array according to one embodiment.
The systems and methods detailed herein generally include magnetic resonance (MR), computed
tomography (CT), nuclear medicine (NM), proton emission tomography (PET), digital radiography
and conventional The present invention relates to diagnostic and medical imaging including
systems such as radiography, mammography, cardiology, angiography or neurology (XR) and
diagnostics and cardiac ultrasound (U / S). In one embodiment, the system relates to large area
array monitoring or imaging systems of the type used for ultrasound or x-ray analysis, and more
particularly to systems and methods that combine high density transducer arrays with
processing circuitry.
In one embodiment of the present system, an organic interposer substrate is used to support
both the ASIC and cMUT in a flip chip connection. The advantages of such a configuration
include the flexibility of attaching the components separately, which allows for the screening of
known good devices and removes the routing bottleneck from the surface of the ASIC.
A further embodiment includes the stacking of tileable modular sensor arrays incorporating an
organic interposer. The modules can be arranged so that they are next to each other, such as
within a few hundred micrometers, thereby reducing the gap between the modules and building
the sensor coverage to be extended. The organic interposer in each module provides an
interconnection between one or more sensor arrays on one side and one or more interface
integrated circuits on the opposite side. The communication mechanism of the modular array
with the external control system can be completed using an input / output connector such as a
ball grid array connection on the back of the interposer. These modules may themselves be tiled
and mounted on a rigid or semi-rigid substrate, which may be glass, ceramic or other similarly
rigid material. This substrate also serves as a routing substrate for communicating the module to
the control system.
A system according to one embodiment provides a large area array of sensor electronics that
integrates sensors seamlessly across the front of the array. This is a difficult task because of the
need to derive electrical signals from the control integrated circuit of the sensor / integrated
circuit assembly. Also, the large number of connections between the sensor array and the control
electronics require fine pitch routing techniques.
FIG. 1 shows an exemplary ultrasound monitoring system 100, in this example one of the types
used for medical imaging, a relatively light, probe unit 110 suitable for handheld applications.
Have. More generally, embodiments of the present invention generally include, but are not
limited to, acoustic monitoring or imaging systems that incorporate large arrays of transducers.
System 100 according to one embodiment includes a probe unit 110 coupled to system console
120 by a multi-channel cable 130 and a display 140 coupled to console 120. The probe unit 110
comprises a transducer assembly 101 having an array 102 of transducer cells 103, a connector
105, a plurality of application specific integrated circuits (ASICs) 106, and an interconnect
structure 107. The console 120 includes a system controller 122, a main beam former 124, an
image processor 126, and a scan converter 127. The array 102 of transducer cells comprises a
plurality of transducer sub-arrays 104 including the same number of transducer cells 103
arranged in columns and rows, respectively. An exemplary transducer sub-array 104 is shown in
the plan view of FIG. In other embodiments, transducer cells 103 are arranged in a pattern that is
compatible with imaging applications. For example, the pattern can be made into geometric
shapes such as hexagonal or octagonal.
Each sub-array 104 is coupled to a corresponding application specific integrated circuit (ASIC)
106 via connector 105. The term processing circuitry, as used herein, refers to various types of
analog or digital circuitry, including system 100, that perform signal processing functions
common to imaging and surveillance systems. For example, circuitry disposed within the probe
unit or system console, such as an image processor, should be understood to include processing
circuitry that supports functions such as amplification, filtering, beamforming or image
processing. The illustrated embodiment specifies the location of such circuits, but this is not at all
limiting. The circuitry disposed in the system console can be partially or completely integrated in
the probe unit, and the circuitry in the probe unit can be disposed in the console. Moreover,
some embodiments that incorporate novel features may not require a console.
Information is communicated between the probe unit 110 and the system console 120 via a
cable 130 coupled between the probe unit line connector 119 in the probe unit 110 and the
console line connector 129 in the system console 120. .
Within system console 120, system controller 122 is coupled to beamformer 124 and image
processor 126 and is also electrically coupled to ASIC 106 within probe unit 110 to provide
timing signals necessary for operation of system 100.
The ASIC 106 generally provides an electronic transmit signal to the sub-array 104 of
transducers to generate an ultrasonic pressure wave, here indicated by the ultrasonic line 142,
which is a survey of the object 141 under investigation It can be returned to the array as a
reflection 144 from area 146. A main beam former 124 is coupled to scan converter 127 to form
an image for display 140.
1 and 2, the plan view of FIG. 2 shows a transducer array 102 comprising a plurality of
transducer modules 210, wherein the modules 210 are formed in the subarray 104 or
transducer cells 103 along row xi and column yj It also comprises a corresponding ASIC 106
coupled to the transducer cell 103 via the interconnect structure 107. In one embodiment,
transducer array 102 is functionally compatible with other transducer assemblies, module 210 is
functionally compatible with other modules, and transducer cell 103 is functional with other
transducer cells. Compatible with Each module 210 comprises a sub-array 104 of transducer
cells 103, the cells 103 being arranged in row x and column y, such that sub-array 104 forms a
module 210, these modules along row x and column y A large array 102 is formed having
transducer cells 103 arranged therein. Row x and column y as well as module 210 extend along a
plane, and in some embodiments, all cells 103 are coplanar. In another embodiment, cells 103
form an array 102 having a curvature with respect to the surface. Each module 210 comprising a
sub-array of transducers and a corresponding ASIC 106 is coupled to the interconnect structure
107 to form a transducer assembly 101.
Referring to the transducer assembly 300 of FIG. 3, this is similar to the transducer assembly
101 of FIG. 1 and has one or more sensors 305, 310, each having a plurality of transducer cells
315 forming an array. According to one embodiment, the assembly 300 uses an interposer 325,
such as the HyperBGA interposer manufactured by Endicott Interconnect Technologies of
Endicott, NY, along with a double sided flip chip assembly. In one embodiment, transducer cell
315 is a cMUT. As described herein, transducer cells 315 can be arranged in various sub-arrays
to provide various types of sensing. The sensors 305, 310 are coupled to the interposer 325 by
flip chip bonding, such as by high density bumps 320, so that both sensors can maintain a very
narrow gap 360 between them, thereby providing high quality imaging Providing a dense cMUT
sensor array with the capability and narrow gaps between adjacent dies, creating a transducer
assembly 300. The high density bumps 320 provide electrical coupling between the individual
transducer cells 315 of the sensor array 305, 310 and the interposer 325.
On the opposite side of interposer 325 is another set of high density bumps 335 that provide
electrical coupling from this side of interposer 325 to integrated integrated circuits 340, 345
such as ASICs. Integrated circuits 340, 345 can provide built-in processing capability for
precondition adjustment or processing on sensor data. Interposer 325 provides an electrical
interconnect 330 from bumps 320 on the first side to bumps 335 on the second side, thereby
electrically coupling specific transducer cells 315 to integrated circuits 340, 345. Transducer
cells 315 can be selectively coupled to integrated circuits 340, 345 such that particular cells 315
provide particular data or redundancy of transducer cells 315. In one embodiment, pad 370 can
be utilized as an electrical connector 350 for input and output connections. Although not shown,
pads may also be used for some or all of the bumps 320, 335.
Referring again to FIGS. 1 and 3, the interconnect structures 107, 330 are coupled to transmit
and receive signals between the ASICs 106, 340, each of the ASICs 106, 340 comprising one or
more sub-arrays 104 of transducers. 305 and associated circuitry, for example processing
circuitry coupled by I / O connector 350, within system console 120. According to the
embodiment of FIGS. 3-7, the assembly 300 includes a number of ASICs 106, 340, each of which
is in one or more corresponding sub-arrays 104, 305 having a number of transducer cells 103,
315. Connected
In this example, external input / output (I / O) can provide data and / or processing data from
interposer 325 to computing resources, storage devices, networks and / or other resources such
as display / print mechanisms. There are additional electrical connectors 350, such as balls in a
ball grid array (BGA) that provide electrical coupling to them.
In one embodiment, flip chip bonding is used to enable modularity in the design and manufacture
of the elements of the assembly.
Such designs can be used to decouple ASIC design risks from package risks and to create large
modular arrays. The modular sensor assembly consists of a series of sensor / ASIC modules. Each
of the modules consists of an interposer with the back side acting as an intermediate substrate
for the ASIC and the front side acting as a sensor array.
As the smaller sensor array itself has an improved yield, more sensor arrays improve the yield of
the assembly. However, with more sensor arrays, the gaps between the sensor arrays themselves
somewhat reduce the effective range of the sensor array. These gaps are mitigated by careful
design of the tolerances for interposer and opposing die placement.
An array of sensors and ASICs are coupled to the interposer using a suitable mounting process.
In one example, these dies are bumped using either eutectic solder or high lead solder, but are
not limited to this technique. Other techniques such as anisotropic conductive film (ACF)
attachment, thermocompression bonding, or atomic wafer bonding can be used as well.
Interposer 325 can either be a standard organic interposer, or one with built-in stiffeners, or one
consisting of a ceramic or glass substrate. Signal routing in the interposer serves two purposes:
First, this redistributes the sensor signal connections between the control ASIC and the sensor
array to absorb pitch mismatches between the two arrays. Second, interposer 325 is used to
route signals from the ASIC to the outside world, including power and ground, digital I / O and
analog signal connections.
External communication is provided using connections on the back of the module. Generally,
these can be provided using BGA interconnect technology, but other interconnect technologies
such as thermocompression bonding or anisotropic conductive film (ACF) may be used.
In one embodiment, the module itself is coupled to a rigid substrate to provide planar uniformity
of the sensor array across module boundaries. This substrate may consist of a glass or ceramic
substrate with the routing of signal lines patterned directly on the substrate. The substrate can
also include a suitable board making material such as FR4 with stiffeners to improve stiffness.
A motherboard as a substrate provides bus transmission of signals such as power and ground,
digital I / O and analog signals between modules. The motherboard also enables communication
of these signals to the outside world through appropriate connectors at the edge of the board
Referring to FIG. 4, a simplified flow diagram of process processing of a large area array modular
sensor array is shown. There are several elements of the system, including interposers, integrated
circuits such as ASICs, and sensor arrays. According to one embodiment, at 410, the sensor array
is flip chip bonded to one side of the interposer. Then, at 420, the ASIC is flip chip bonded to the
opposite side of the interposer to form a transducer assembly. At 430, the interposer provides
electrical interconnections between the ASIC and the sensor array. The transducer assembly is
then mounted to the substrate with additional electrical interconnections extending from the
interposer to the substrate. The interposer enables communication from the sensor array and
ASIC to the substrate and external resources, as the substrate includes access to various external
resources such as control circuitry, storage and imaging circuitry, as well as input and output
FIG. 5 shows a further embodiment of a transducer assembly 500 showing a plurality of sensor
arrays 510, 515, 520, 525 flip chip bonded to the interposer 530 by high density bumps 535.
The sensors 510, 515, 520, 525 in this example are transducer arrays, with small gaps
separating the sensors creating a large array size with a small form factor for applications such
as in a probe. Interposer 530 provides electrical coupling or interconnection 560 to various
numbers of integrated circuits 540, 545, 550, 555 via high density bumps 565. The electrical
connections of interposer 530 provide a plurality of connections from sensors to an integrated
circuit, as well as interconnections coupling individual sensors and among the sensors. The
interconnections include coupling of ASIC signals as well as coupling between ASICs. In addition,
the interconnect can also include coupling of multiple signals from the ASIC between the sensor
and / or such components. This also includes external electrical coupling. Connections to external
resources are provided by electrical connections 570, such as BGAs. In this way, the transducer
assembly of the plurality of sensors 510, 515, 520, 525 can be made of modular components,
and then the modular components are combined with other transducer assemblies, and so on
Array can be formed.
Referring to FIG. 6, a large scale transducer array 600 according to one embodiment is shown.
The transducer array 600 consists of multiple tileable modules 610 integrated into a large
transducer array for various applications, such as compression plates for mammography. The
aperture 620 in this example scans the transducer array 600 to extract a signal image to
construct a full image. Array and aperture sizes can be designed according to design criteria. In a
further embodiment, by utilizing raster scanning with apertures for individual imaging
applications, larger transducer arrays can be employed in multiple applications.
In one embodiment, each compression plate implements a mosaic annular array (MAA), and the
annular apertures raster scan to construct a corresponding image. For example, the aperture of
the successful embodiment includes 64 rings with 185 μm cMUT transducer elements. Arrays
are used for B-Mode or transmission imaging. Each plate is constructed from an array of 2.5 cm
× 2.5 cm tileable modules to form a total array size of 25 cm (X) × 20 cm (Y). Larger arrays
also allow larger apertures for raster scanning.
In a further embodiment, the tileable modules are arranged in a pattern or shape that can be
adapted for imaging applications. For example, tileable modules can be geometrically arranged,
such as hexagonal or octagonal arrangement.
7a and 7b show an example of a tileable module configuration for a tileable module 700
including a plurality of transducer arrays 705 forming sensors coupled to the interposer 710 in a
small form factor. There is an integrated circuit 715 coupled to the opposite side of interposer
710. BGA balls such as those shown in FIGS. 3 and 5 are used to couple the tileable module to
the external interface. A plurality of transducer assemblies 705 and a plurality of integrated
circuits 715 sandwich the interposer 710 to provide electrical coupling between the transducer
assemblies 705 and the integrated circuits 715.
In one embodiment, the tileable module is a HyperBGA laminate substrate, and the number of
transducer assemblies 705 exceeds the number of integrated circuits 715. According to one
embodiment, the tileable module is an 8x8 device with 64 transducers, each transducer having
16x16 transducer cells. There are four ASICs, enabling a reconfigurable array having a size of
about 2.5 cm × 2.5 cm.
Referring to FIG. 8, a further transducer assembly is shown. In this example, there are multiple
tileable modules 805, 810 coupled together and coupled to the substrate 860. The tileable
modules 805, 810 are mounted on the substrate 860 with minimal spacing between modules to
reduce the gap. In one embodiment, the substrate is a rigid substrate, such as FR4 or glass, which
can conduct signals. In another embodiment, the substrate is a motherboard. The back side of the
substrate 860 includes electronics for controlling the transducer array via controller electronics
865, which may be local storage of configuration data 870 and of the receiving channel via
imaging electronics 875. Adapt to aspects such as buffering. The electrical connection to external
resources in one embodiment is a cable or jumper from substrate 860, either directly or through
a connector on substrate 860.
The tileable module 805, 810 includes a plurality of transducer arrays 815 each including a
plurality of transducer cells 820. The individual transducer arrays 815 are separated by a
minimum dimension gap 830 of the transducer assembly sufficient to allow flip chip balls 825 to
couple between the transducer array 815 and the interposer 840. There is also a minimal gap
835 between adjacent tileable modules 805 and 810 to maintain a small form factor and
maintain functionality. Integrated circuit 850 is coupled to interposer 840 on the side opposite
transducer array 815. Integrated circuits, such as reconfigurable array chips, are coupled to the
interposer by flip chip ball bonds 845. The flip chip ball bond of the transducer array may be the
same or different than the flip chip ball bond of the integrated circuit.
The interposer is coupled to the substrate 860 so that the tiling modules 805, 810 and the
various electronic components and / or various available via the I / O connections 880 mounted
to the substrate 860 There are BGA balls 855 designed to provide an electrical coupling between
the electronic components. The embedded electronics allow for the integration of some of the
electronics of FIG. 1, resulting in a more robust probe unit.
Referring to FIG. 9, tileable modules 905, 910, such as those shown in the other figures, are
electrically connected to the motherboard 925 by BGA connections 935. In this example, the
motherboard 925 is coupled to a connector 915 that provides an interface to a cable connection
920 that provides an interface to external resources. Such an arrangement allows the tileable
module and its sensor / ASIC to communicate with external resources.
FIG. 10 shows a further embodiment in which the motherboard 1025 and the tileable module are
present in the enclosure 1020 with coupling to the connector 1030 such that the entire
assembly is sealed. The sensors, ASICs and interposers that form tileable modules may be any of
the modules detailed herein. The cable 1035 is connectable to the connector 1040 such that the
entire sealed unit is modular and portable.
11a and 11b show a few micrometer (μm) spacing between dies and between modules
according to one embodiment. The gap dimensions in the example of FIG. 11a are: cMUT pitch
1105 is approximately 185 micrometers, placement 1120 between chip edges is approximately
100 micrometers, dicing / chipping tolerance 1115 is approximately 50 micrometers, , CMUT
center to cMUT edge 1110 is about 92.5 micrometers, and cMUT center to cMUT center
indicates a total of other dimensions of about 385 micrometers.
Referring to FIG. 11 b, the placement 1130 between module edges is about 100 micrometers, the
placement 1135 between chip edges and substrate edges is about 0 micrometers, and dicing /
chipping tolerance 1115 is It is about 50 micrometers, between cMUT center and cMUT edge
1110 is about 92.5 micrometers, and between cMUT center and cMUT center is about 385
Referring to FIG. 12, an SEM image demonstrating the conceptual design is shown.
As shown, sensor device 1210 is flip chip connected on top of the internal surfaceless (NIP)
organic interposer 1240 and integrated circuit device 1250 is flip chip connected on the back of
interposer 1240. In one embodiment, the organic interposer 1240 comprises
polytetrafluoroethylene (PTFE), also known as the Teflon® trademark. The PTFE tip carrier or
interposer 1240 is a mechanically reliable organic material with good conductivity properties. In
one embodiment, the organic interposer consists of polytetrafluoroethylene (PTFE) reinforced
with a copper-invar-copper (CIC) core to control flatness and coefficient of thermal expansion
(CTE). The sensor device 1210 is flip chip connected to the interposer 1240 and does not use an
In one embodiment, sensor device 1210 is a grooved sensor having posts 1285 electrically
coupled to organic interposer 1240 by balls 1285. The grooved sensor device 1210 design
provides enhanced mechanical stability. In one embodiment, the sensor device is a grooved
cMUT flip chip bonded to a PTFE tip carrier.
According to one embodiment, there is a minimum gap 1220 between adjacent sensors 1210 to
accommodate multiple sensors. There is a pitch 1230 of the sensor's electrical interconnections,
which in this example is 185 micrometers, and the pitch 1260 of the integrated circuits 1250's
electrical interconnections is 150 micrometers. Solder balls 1270 are also shown on the back.
Although the backside ASIC 1250 die is not thinned in this figure, in one embodiment of the
design this die has a 250 μm thickness that allows I / O connector 1270 to be coupled to a
substrate (not shown). It should be noted that
In more specific details of one embodiment, a grooved cMUT device is attached to the top surface
of the laminate interposer. The top of the column 1280 is attached to the active area of a silicon
device that is only about 22 μm thick. A grooved cMUT device 250 μm long and 85 μm square
pillars is attached to the Teflon based organic interposer using flip chip connection. The cMUT
columns are bumped with eutectic Sn-Pb solder. One example includes a bumped grooved cMUT
device, in which an under bump metallurgy (UBM) structure is deposited on the pillars and then
bumped with solder. This bumped grooved device is then flip chip soldered to the top surface of
the laminate interposer. When these bumped slotted devices are attached to the interposer, the
cMUT devices remain flat and separated by about 100 μm. On the backside of the interposer, an
ASIC chip with a pitch of 150 μm and over 4000 I / Os are flip chip connected to create an
underfill. Also, ball grid array (BGA) spheres are attached to the back and BGA balls are used to
attach the modules to the board.
One embodiment of a test system 1300 used to obtain wafer map 1360 is shown in FIG. 13 and
cMUT wafer 1302 is coupled to probe card 1305 which is part of probe station 1310. Probe
station 1310 is coupled to various sources and measurement devices. In this example, there is a
voltage bias 1320 coupled to the probe station 1310 and an AC coupler 1325 coupled to the
probe card 1305. The computing device 1340 is communicatively coupled to the probe station
1310, such as via a general purpose interface (GPI). Computer 1340 is also communicatively
coupled to impedance analyzer 1330, such as via GPI. Impedance analyzer 1330 is also coupled
to AC coupler 1325. Computer 1340 processes information that may include metrics to obtain
wafer map 1360.
In another embodiment, the interposer can be tested by applying an analog waveform to the
common electrode and looking for shorts in the transducer assembly and opens in the signal BGA
A detailed flow diagram illustrating the processing of a large sensor array is shown in FIG.
The main elements of the module assembly of this embodiment include cMUTs, ASICs, and
interposers. Each of these elements has specific processing steps that can be undertaken prior to
integration into the module assembly. Furthermore, the processing steps of integration in this
example are also shown. It is noted that in other embodiments, there may be different and some
steps in the process. It should be understood that these steps are just an example, that there may
be additional and omitted steps, and that there is no specific sequence if not mentioned.
For cMUT processing, at 1402, cMUT wafers are prepared and inspected to ensure that there are
no major defects and that there is a good population of good products. At 1404, solder bumps
are provided to the cMUT wafer by any of the methods detailed herein. An optional step will be
to inspect the bumped die to ensure that the bumps are properly applied and conductive. Then,
at 1408, the wafer is subjected to dicing and sorting of the wafer. In one embodiment, a waffle
pack is used.
For integrated circuit processing, such as ASIC, the wafer is generally inspected at 1410 and then
solder bumped at 1412. Solder bumping may be any of the types detailed herein. At 1414, the
wafer is thinned to the desired thickness relative to the application criteria. The wafer may
optionally be inspected to ensure that the process has not damaged the wafer. Next, at 1418, the
IC wafer is subjected to dicing and wafer sorting. An optional waffle pack can be utilized with the
IC wafer.
At 1420, the interposer is fabricated according to design specifications, or otherwise procured
for application requirements. In some embodiments, interposers are more common, while others
require special designs. At 1422, the top and bottom pads of the interposer can be ENIG plated.
An optional electrical test may be performed. At 1426, the interposer is sorted upon receiving a
particular analysis, such as flatness measurement. Further analysis at 1428 includes
measurement and sorting of interposer dimensions.
Then, at 1430, the cMUT, ASIC and interposer become a module assembly. At 1450, the module
assembly begins distributing flux to the backside of the interposer. A ball grid array (BGA) ball is
then placed on the back at 1452. At 1454, the bumped ASICs are aligned on the interposer BGA
balls. At 1456, reflow is performed to remove the flux. An optional electrical test can be
performed on the bump bonded ASIC. At 1458, the underside of the interposer backside is
provided to ensure that the components are in place. At 1460, the flux is distributed on the top
surface of the interposer, and at 1464 cMUTs with bumps are aligned on the top surface of the
interposer. At 1466, reflow is performed to remove the flux. An optional test can be performed to
check the electrical interconnections. In this configuration, a very thin device with a thickness of
only 50 μm is used to construct an active cMUT die. The back side consists of a peripheral
trench surrounding a column with dimensions of 90 μm × 90 μm × 200 μm. On the tips of
the pillars, 70 μm diameter under bump metallization (UBM) pads are deposited along with low
melting point solder bumps. This fragile device eliminates the need for an underfill due to the
high offset effect of the long pillar (200 μm) interconnect with solder ball height that results in a
PTFE interposer compliant property and low stress interconnect design. Can be attached to the
The interposer can also provide communication between individual adjacent integrated circuits,
which provides cohesive operation of the entire system.
The advantages of this module include a modular assembly that is easy to rework, a small gap,
near perfect distributed sensor array, and uniform coplanarity across the array.
This modular configuration allows modular assembly, connection between ASICs in interposer,
double-sided flip chip packaging, module mounting on glass, cMUT sensor, flat to ensure close
dimensions (X, Y, Z) Allows tilingable arrays with large substrates, small sensors that can be tiled
/ reworked, and stacked / small cMUTs (for high yield).
The same interconnect layer is used to provide connections to elements and connections to I / O.
In a single module with multiple ASICs in this example, all generally identical I / O (analog I / O
and digital I / O) to significantly reduce the number of I / O connections required on the module.
Share). In one embodiment, the interconnect layer provides the connection between the ASICs in
the module.
In a further embodiment, the ASIC cell is made smaller (at a different pitch from the array) to
match both I / O around the die as well as BGA balls outside the die. In one embodiment, signals
are routed through the die to reduce the required routing in the interposer. The module may
consist of multiple smaller cMUT dies to improve yield (by sorting the dies prior to placement on
the interposer) and to reduce the effects of CTE mismatch. One further advantage is that underfill
is not used on the cMUT surface to remove fillets and place the dies in close proximity.
The die of the ASIC can be thinned to reduce fillets, thereby reducing the keepout area around
the ASIC and expanding the unit cell size. The die is thinned so that the BGA balls can be cleaned
on the back side. A high melting point ball can be used on the integrated circuit, followed by a
low melting point ball on the transducer assembly. The solder bumping ball may be any one of
solder jet, electroplating, vapor deposition, plated plastic spheres, solder ball transfer or other
suitable solder technology.
A further aspect includes stacking additional dies on the integrated circuit surface using through
silicon vias (TSVs) in the dies. Another aspect includes the step of providing an additional layer of
ceramic between the interposer and the transducer assembly to relieve stress in the transducer
In one embodiment, the gap between modules is less than or equal to 100 μm, and the die is at
the same height as the substrate.
Another aspect is to have a module that can be connected with a socket or solderable BGA.
According to one aspect, the system is a field replaceable unit (FRU) with modular design and
connectivity. One method of assembly involves having a large area array to obtain high yield and
inspecting each module prior to assembly. The method includes a transducer assembly that is
replaceable due to the lack of underfill, and the ASIC has a high melting point ball to allow
additional reflow.
In one aspect, an anisotropic conductive film (ACF) is used to attach the interposer to the
integrated circuit and / or the transducer assembly.
For example, the interposer can be a silicon interposer substrate having a BGA coupled to the
In one embodiment, the interposer is a glass board with routing on the board. In one
embodiment, there is a large array (20 cm × 25 cm or more) of individual tileable modules.
Further details regarding interposers and tiled transducers are described, for example, in US Pat.
No. 7,375,420, assigned to the present assignee, which is incorporated herein by reference.
In one embodiment, the ultrasound monitoring system comprises an array of transducer cells
arranged in columns and rows and having a first pitch along a first direction along a first plane. It
has a probe unit and is formed. An integrated circuit including an array of circuit cells is formed
along a second plane parallel to the first plane. The circuit cells are spaced apart along the first
direction at a second pitch smaller than the first pitch. The first transducer cell has a connection
to the first circuit cell with the first circuit cell and is vertically aligned along a direction
perpendicular to one of the faces; The second transducer cell is offset from the perpendicular
orientation with respect to the position of the second circuit cell so that it does not overlap on
the second circuit cell. A connection is formed between the array of transducer cells and the
array of circuit cells to the first circuit cell of the first transducer cell, and configured to connect
the second transducer cell to the second circuit cell Connected subsystems are deployed. An
interconnect structure is disposed to provide an electrical connection between the integrated
circuit and the processing circuit.
In one embodiment, one method of forming an ultrasound imaging system having transducer
circuitry comprises: providing an array of transducer cells along a first plane at a first pitch along
a first direction; Providing an integrated circuit device comprising an array of circuit cells and a
plurality of I / O pads formed along an edge of the integrated circuit device. The circuit cells are
formed along the first direction at a second pitch smaller than the first pitch, and the first
transducer cells are formed on the first circuit cells along a direction perpendicular to the first
plane. The second transducer cells are offset relative to the positions of the first transducer cells
and the first circuit cells so that the second transducer cells do not overlap on top of the second
circuit cells. The redistribution system is configured to route the connection between the second
transducer cell and the second circuit cell. An interconnect structure is provided that comprises
an array of connectors. The connector provides a connection between the I / O pads of the
integrated circuit structure in the plurality of transducer modules and the electronic components
of the ultrasound imaging system.
One aspect discloses a module, such as a smaller size integrated circuit is different from the
interposer, or a module incorporating multiple integrated circuits within the module.
Further aspects disclose the interconnection between dies in a module and the grouping /
busting of signals from pads to reduce the overall I / O of the package.
The prior art does not generally disclose interconnect structures / interposers made of Teflon®
or other rigid organic substrates rather than modular structures.
The present method and system utilize existing manufacturing techniques to group / bus signals
in the interposer, a lower cost manufacturable transducer whose integrated circuit is smaller
than the interposer to allow BGA bonding. Provide an assembly.
This design further provides a smaller cMUT without underfill.
A further example is a large area reconfigurable imaging array developed with co-integrated
cMUTs and control electronics that can be used as a compression plate configuration.
Such systems can be used in conjunction with x-ray mammography replacement and / or such
mammography such as ultrasound specificity for dense tissue.
This device is a 2.5 cm 2D tileable module with more than 16,000 transducer subelements
separated by a pitch of 185 μm in the X and Y dimensions. As a demonstration, a multi-row,
one-dimensional array was designed and fabricated using cMUT and multiplex electronics. The
grooved cMUT was attached to the laminate interposer as part of a tileable module. This tileable
module configuration showed reduced productivity, reliability, acoustical planarity, and spacing
between tiles and cMUT chips.
Another embodiment is a standardized package platform that can be used for multiple
applications and embodiments. Although the described embodiment is for a cMUT sensor, a PZT
crystal can be implemented instead of a cMUT.
Although a number of system embodiments have been shown and described, the invention is not
so limited. Many modifications, variations, substitutions and equivalents will occur to those
skilled in the art without departing from the spirit and scope of the present invention.
Reference Signs List 100 ultrasonic monitoring system 101 transducer assembly 102 transducer
array 103 transducer cell 104 transducer sub array 105 connector 106 ASIC 107 interconnect
structure 110 probe unit 119 probe unit line connector 120 console 122 system controller 124
main beam former 126 image processor 127 scan converter 129 Console Line Connector 130
Multi-Channel Cable 140 Display 141 Object 142 Ultrasonic Line 144 Reflector 146
Investigation Area 210 Module 300 Transducer Assembly 305 Sensor 310 Sensor 315
Transducer Cell 320 High Density Bump 325 Interposer 330 Electrical Phase Connections 335
High Density Bump 340 IC 345 IC 350 I / O Connection 360 Gap 400 Flowchart 420 Flowchart
430 Flowchart 440 Flowchart 500 Flowchart 500 Transducer Assembly 510 Sensor 515 Sensor
520 Sensor 525 Sensor 530 Interposer 535 Bump 540 Chip 545 Chip 550 Chip 555 Chip 565
Bump 570 BGA 600 Transducer Assembly 610 Tiling Module 620 Opening 700 Tiling Module
705 Integrated Device 710 Interposer 715 IC 805 Tiling Module 810 Tiling Module 815
Transducer Array 820 Transducer Cell 825 Flip Chipball 830 transformer Deducer Assembly
Gap 835 Module Gap 840 Interposer 845 Flip Chip Ball 850 IC 855 BGA 860 Substrate 865
Control 870 Storage 875 Imaging 880 I / O 905 Tilingable Module 910 Tilingable Module 915
Connector 920 Cable 925 Motherboard 935 BGA 1020 enclosure 1025 motherboard 1035
connector 1105 cMUT pitch 1110 cMUT center to cMUT edge 1115 dicing / chipping tolerance
1120 chip edge to chip edge placement 1130 module to module edge placement 1135 Chip
Edge to Substrate Placement 1210 Grooved cMUT 1220 Gap 1230 Gap 1240 Ntapoza 1250
ASIC 1260 gap 1270 BGA ball 1300 test system 1302 cMUT wafer 1305 probe card 1310 probe
station 1320 voltage bias 1325 AC coupler 1330 impedance analyzer 1335 GPIB 1340 PC 1345
GPIB 1360 wafer map
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