Patent Translate Powered by EPO and Google Notice This translation is machine-generated. It cannot be guaranteed that it is intelligible, accurate, complete, reliable or fit for specific purposes. Critical decisions, such as commercially relevant or financial decisions, should not be based on machine-translation output. DESCRIPTION JPH0583160 [0001] BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a de-emphasis apparatus for converting an emphasised digital audio signal into a digital signal with flat frequency characteristics. [0002] 2. Description of the Related Art In general, a de-emphasis system comprises an analog filter. [0003] Hereinafter, an example of the above-described conventional de-emphasis apparatus will be described with reference to the drawings. [0004] For example, according to the "Satellite Broadcast Reception Guide 1983.5" (NHK General Office of Sales and Marketing Department), in television satellite broadcasting, the emphasis characteristic (CCIR) in Fig. 7 (a) is obtained by the pre-emphasis circuit in Fig. The audio signal of which high range is enhanced in Rec. 405-1 standard and transmitted as a digital signal by the PCM subcarrier system is D / A converted at the receiving side and converted back to an analog signal, as shown in FIG. The original flat frequency characteristic is restored by the de-emphasis circuit shown in FIG. 08-05-2019 1 [0005] However, in the configuration as described above, deterioration in quality due to analog processing and variation in accuracy due to component deviation occur. In addition, when it is desired to convert an emphasized digital audio signal into a flat frequency characteristic and treat it as digital, D / A conversion and A / D conversion must be performed before and after the de-emphasis device, so the scale of the device Problem of increase of [0006] In order to solve these problems, it is necessary to process the digital audio signal with emphasis as it is and convert it into a flat frequency characteristic as it is digital. However, in the prior art, the scale of the apparatus becomes large. Become. [0007] SUMMARY OF THE INVENTION The present invention is intended to solve the above-mentioned conventional problems, and it is an object of the present invention to provide a small-scale deemphasis apparatus that performs digital signal processing on digital signals with emphasis on digital as they are. . [0008] SUMMARY OF THE INVENTION A de-emphasis apparatus according to the present invention is a method for emphasizing an N-ary digital speech signal (N: integer) having a transfer function H (z) = (b0 + b1z-1) / ( 1-a1 z-1) (a1, b0, b1: constant) иии A first-order IIR (infinite impulse response) filter represented by (Expression 1), and all the absolute values of its constants a1, b0 and b1 are It is configured by a filter that is a sum of or a difference of N powers or two N powers. [0009] With this configuration, multiplication processing in digital signal processing is realized by a simple operation such as shift. As a result, the de-emphasis device of the present invention can perform signal processing as 08-05-2019 2 digital while reducing the size of the device. [0010] EXAMPLES Specific examples will be described in detail below. [0011] FIG. 1 shows a functional block diagram of a first embodiment of the de-emphasis apparatus of the present invention. The de-emphasis apparatus of the present invention receives an emphasis-based N-ary digital speech signal (N: integer) as an input. In the present embodiment, CCIR Rec. A binary digital audio signal complemented by a sampling frequency of 32 kHz and having an emphasis characteristic of the 405-1 standard is input. [0012] In FIG. 1, reference numeral 1 denotes a multiplication means which outputs an input multiplied by 2-1. Reference numeral 2 denotes a multiplication means which outputs an input multiplied by 2-5. Reference numerals 3 and 4 denote addition means for outputting the sum of two inputs. Reference numeral 5 denotes delay means for outputting an input delayed by one clock of the same frequency as the symbol rate of the input signal of the de-emphasis apparatus. [0013] 08-05-2019 3 The multiplying means 1 multiplies the output of the adding means 3. The multiplying means 2 multiplies the output of the delay means 5. The addition means 3 adds the input of the deemphasis device and the output of the delay means 5. The addition means 4 adds the output of the multiplication means 1 and the output of the multiplication means 2. The delay means 5 delays the output of the multiplication means 1. The output of the de-emphasis device is the output of the multiplying means 4. 0The output at ~ 16 kHz is shown in FIG. The deviation is less than 0.48 dB. [0014] The above configuration is a first-order IIR filter whose transfer function is expressed by equation 1, and the constants of equation 1 are as follows: a1 = 2?1, b0 = 2?1, b1 = ?2-6 It will be realized. Thus, by making all the absolute values of the constant of Equation 1 into a power of 2, the absolute values of the coefficients of multiplication in the multiplication means of the de-emphasis apparatus become all powers of 2. This can be done by simple digital processing such as shifting. [0015] FIG. 2 is a circuit diagram of an embodiment in which the de-emphasis apparatus of FIG. 1 is realized by hardware, and this will be described. In the description, one sample of the input of the de-emphasis device is n bits (n: integer). [0016] Reference numerals 23 and 24 denote addition circuits which add and output two inputs. A delay circuit 25 outputs an input delayed by one clock of the same frequency as the symbol rate of the input signal of the de-emphasis apparatus. Reference numeral 26 denotes an inverting circuit which outputs an inverted version of 0 and 1 of each bit of the input. [0017] In the addition circuit 23, the multiplication by 2-1 times that of the multiplier 1 of FIG. 1 is performed from the upper bits a (n-1), a (n-2),..., A (1), a (0) The input a of the de-emphasis 08-05-2019 4 device is shifted downward by 1 bit to a (n-1), a (n-1), a (n-2),..., A (1), a (0) And the output b of 25 (b (n-1), b (n-2),..., B (1), b (0), b (-1) from the high order bit) Equivalent to using one that is shifted by 1 bit to b (n-1), b (n-1), b (n-2), ..., b (1), b (0) Do. [0018] Here, the fact that the most significant bit before shift processing is inserted into the most significant bit takes into consideration that the signal is a two's complement. [0019] In addition, multiplication by (-2-5) times of multiplier 2 in FIG. 1 is performed in the addition circuit 24 by inverting the 0 and 1 of each bit by the inversion circuit 26 in the addition circuit 24 and then shifting downward 5 bits to the high order From bit to * b (n-1), * b (n-1), * b (n-1), * b (n-1), * b (n-1), * b (n-1), * b (n-2),..., * b (4) (* represents inversion) and 23 outputs are input. [0020] Here, the fact that the most significant bit before shift processing has been inserted from the most significant bit to the fifth significant bit takes into consideration that the signal is a two's complement. [0021] Thus, in the first embodiment, the usual multiplication circuit is not necessary. This is because the multiplication coefficients are all powers of 2 with respect to the input of the binary digital signal, because the absolute values of the constants a1, b0 and b1 of the transfer function represented by the equation 1 are all 2 It originates in the fact that it is a power (a1 is 21, b0 is 2-1, b1 is -2-6). [0022] The above-described de-emphasis apparatus can be realized not only by a circuit but also by means of calculation such as a microcomputer or DSP. 08-05-2019 5 A second embodiment in which the de-emphasis apparatus of FIG. 1 is realized by software will be described with reference to the flowchart of FIG. In addition, since it is the same structure about the structure shown and demonstrated in FIG. 1, the detailed description is abbreviate | omitted. [0023] Reference numeral 31 denotes a multiplication step in which an input multiplied by 2-1 is used as an output. The reference numeral 32 denotes a multiplication step in which an input multiplied by 2-5 is output. Reference numerals 33 and 34 denote addition steps for outputting the sum of two inputs. Reference numeral 35 denotes a delay step of outputting an input delayed by one clock of the same frequency as the symbol rate of the input signal of the de-emphasis apparatus. [0024] In the multiplication step 31, multiplication is performed by shifting the input downward by one bit. In the multiplication step 32, multiplication is performed by inverting 0 and 1 for each bit of the input and then shifting downward 5 bits. [0025] As a result, in the embodiment of FIG. This is because the absolute value of the multiplication coefficient is a power of 2 with respect to the input of the binary digital signal, and all of the absolute values of the constants a1, b0 and b1 of the transfer function represented by the equation 1 are all It is attributed to the fact that it is a power of 2 (a1 is 2-1, b0 is 2-1, b1 is -2-6). [0026] 08-05-2019 6 As described above, according to the first embodiment and the second embodiment, the absolute values of the constants a1, b0 and b1 of the transfer function represented by the above equation 1 can be obtained with respect to the input of the binary digital audio signal subjected to emphasis. Since the IIR filter is a power of 2 in all, while reducing the size of the device, it is possible to perform digital signal processing and convert it into a digital signal with flat frequency characteristics. [0027] Next, a specific example of the de-emphasis apparatus in which the absolute value of b1 is the sum of two powers of 2 will be described. [0028] A third embodiment will be described in which the constant of the equation 1 is represented by a1 = 2?1, b0 = 2?1, and b1 = ?2?6-2-7. In order to realize this de-emphasis apparatus, the coefficient of the multiplication means 2 may be set to -2-5-2-6 in the functional block diagram of the first embodiment shown in FIG. This corresponds to inverting the input and then adding the one shifted by 5 bits and the one shifted by 6 bits respectively. The other configuration is the same as the configuration described in the first embodiment, so the detailed description thereof is omitted. 0The output at ~ 16 kHz is shown in FIG. The deviation is less than 0.32 dB. [0029] A fourth embodiment will be described in which the constant of the equation 1 is represented by a1 = 2-1; b0 = 2-1; b1 = -2-6-2-8. In order to realize this de-emphasis apparatus, the coefficient of the multiplication means 2 may be set to -2-5-2-7 in the functional block diagram of the first embodiment shown in FIG. This corresponds to inverting the input and then adding the one shifted by 5 bits and the one shifted by 7 bits. The other configuration is the same as the configuration described in the first embodiment, so the detailed description thereof is omitted. 0The output at ~ 16 kHz is shown in FIG. The deviation is less than 0.39 dB. 08-05-2019 7 [0030] In the first embodiment and the second embodiment, the absolute values of the constants a1, b0 and b1 of the equation 1 are all powers of 2. However, as in the third embodiment and the fourth embodiment A power of 2 or a sum or difference of two powers of 2 can represent finer values, and the accuracy is further improved. In the third and fourth embodiments, the size of the device is larger than that of the first and second embodiments, but the size of the device is reduced by performing multiplication and the like by shifting. The same effect as the first and second embodiments can be obtained. The constants a1, b0 and b1 of the above equation 1 may be determined while considering the required accuracy and the scale of the apparatus. [0031] In the present embodiment, CCIR Rec. Although the binary digital audio signal whose complement of 2 of the emphasis characteristic of the 405-1 standard is an input is used as an input, even when an N-ary digital audio signal (N: integer) is input, the constant a1, b0, b1 The same effect as that of the present embodiment can be obtained by making the absolute values all N's power or the sum or difference of two N's power. [0032] As described above, the de-emphasis apparatus according to the present invention receives an emphasised N-ary digital speech signal (N: integer) as an input, and the absolute value a 1 of the transfer function constant represented by the above equation 1 By making b0 and b1 all N powers or addition or subtraction of two N powers, it is possible to reduce the size of the device while performing digital signal processing with emphasis on the digital audio signal subjected to emphasis and making it flat. It can be converted to a signal of frequency characteristics, and degradation of quality due to analog processing can be prevented. 08-05-2019 8

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