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JPH01105997

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DESCRIPTION JPH01105997
[0001]
[Industrial Field of Application Koni's invention relates to a screen display device capable of
performing level display of an analog input signal at high speed. 2. Description of the Related Art
As shown in FIG. 5, a conventional screen display apparatus comprises a control unit 51
comprising a CPU operating according to software, an image buffer memory (V-RAM) 52, an
image signal generating circuit 53 and a display screen 54. It consists of For example, when
displaying the character rAJ on the display screen 54, the control unit 51 calculates the address
of the image buffer memory 52 corresponding to the position on the screen, and the character
code corresponding to the character rAJ (for example 40H). Write). Further, for example, when
displaying the level of the audio signal graphically, the audio signal is first binarized by the
external A / D converter. Then, the control unit 51 receives the binarized level information,
calculates the address of the image buffer memory 52 corresponding to the position on the
screen according to the level information, and the character code corresponding to the display
mark in the address. Perform the action of writing [Problems to be Solved by the Invention] In
the above-described conventional screen display device, all display operations are performed
through the control unit 51 including a CPU, and thus the level of a signal changing at high
speed is displayed. In the case, there was a time delay from the input of the signal to the display,
and the display did not respond quickly to changes in the signal level. A main object of the
present invention is to provide a screen display device capable of displaying a level change of an
analog input signal at high speed without delay. [Means for Solving the Problems] The screen
display apparatus according to the present invention is a screen display apparatus for graphically
displaying the level of an analog input signal, and comprises conversion means, storage means,
display means, and control means. It is a thing. The conversion means is provided with output
terminals of a plurality of digits, and digitally converts an analog input signal to derive an output
corresponding to the level of the analog input signal from each output terminal. The storage
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means comprises a plurality of storage areas for storing the outputs from the output terminals of
the conversion means. The display means is provided with a screen including a level display area
consisting of a plurality of display sections respectively corresponding to the storage areas of the
storage means. The control means causes the display section corresponding to each storage area
of the storage means to perform display corresponding to the storage content of the storage
area. [Operation] According to the screen display device of the present invention, the
predetermined information is written in the corresponding storage area of the storage means
according to the level of the analog input signal, and the screen corresponding to the storage
area in which the information is written A display corresponding to the information is given in
the upper display category.
Since the display operation is performed without passing through the control unit and the like
including the CPU, the level of the analog input signal changing at high speed can be displayed at
high speed without delay. Embodiments of the present invention will be described below with
reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present
invention. In the figure, a control unit 2 comprising a CPU and an A / D converter 3 are
connected to an image buffer memory (V-RAM) 1. The image buffer memory 1 includes a general
display buffer memory 11 controlled by an output to the control unit 2 and a level display buffer
memory 12 controlled by an output from an A / D converter 3. The image signal generation
circuit 4 generates an image signal corresponding to the storage content of the image buffer
memory 1 and causes the display screen 5 to display an image corresponding to the storage
content. The film display buffer memory 11 is used for a general display not requiring relatively
high speed, and the level display buffer memory 12 is used for a high speed required level
display. FIG. 2 is a diagram showing a circuit configuration of the level display buffer memory 12
and the A / D converter 3 in FIG. In the figure, the level display buffer memory 12 includes a
plurality of storage areas M,..., Mn. The display screen 5 includes a plurality of display areas V1
to Vn respectively corresponding to the storage areas M to M (see FIG. 1). On the other hand, the
A / D converter 3 includes an A / D conversion unit 31 including a plurality of resistors R and a
plurality of operational amplifiers Q and ~Qn and a write inversion buffer 32 including a plurality
of inverters I and ~In. In the A / D conversion unit 31, the voltage V is divided into a plurality of
reference voltages V and ~Vo by the resistors R connected in series. The reference voltages V and
Vo are respectively applied to positive input terminals of the operational amplifiers Q and Qn,
and the input voltage Vin is commonly applied to negative input terminals. The outputs of the
operational amplifiers Q1 to Qo are transferred to the corresponding storage areas M and Mo of
the level display buffer memory 12 via the inverters I to Io of the write / invert buffer 32 and the
write data lines W and -W. Each will be given. The outputs from the storage areas M1 to Mo of
the level display buffer memory 12 are applied to the image signal generation circuit 4 through
the read data lines R1 to R. The operation of the circuit of FIG. 2 will now be described. In each of
the operational amplifiers Q to Qn, when the input voltage Vin applied to the negative input
terminal exceeds the basic voltage V to .Vrl applied to the positive input terminal, the output
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voltage becomes 0 [V].
Therefore, for example, when v2 く vin <V, the output voltages of both the operational amplifiers
Q + and Q2 become 0 [V], and the output voltages of the operational amplifiers Q3 to Qn become
the power supply voltage. Since these output voltages are applied to the level display buffer
memory 12 through the write inversion buffer 32, the corresponding data is stored in each of the
storage areas M and ~ Mo (M +, M2 '+ M3, -, Mn-+. Mn)=(1,1,O,−,0,0)となる
。 These data are manually input to the image signal generating circuit 4 through the read data
lines R7 to Ro. Thus, the CPU does not intervene in the image signal conversion of the input
voltage Vin, and therefore the delay time is reduced. The image signal generation circuit 4
generates an image signal corresponding to the storage content of the level display buffer
memory 12 and displays a display area V on the screen 5 corresponding to the storage areas M1
and M2 in which data of "1" is stored. ,, V2 to make a predetermined display. FIG. 3 is a block
diagram showing another embodiment of the present invention. This embodiment is intended for
screen display of a VTR (Video Tape Recorder). In this embodiment, the level display buffer
memory 12 is divided into two systems of a first buffer memory 12a and a second buffer
memory 12b. Corresponding to this, the A / D converter 3 is also provided with two systems of
the left sound A / D converter 3a and the right sound A / D converter 3b. The left voice A / D
converter 3a is supplied with stereo left voice human power, and the right voice A / D converter
3b is supplied stereo right voice human power. The output of the left audio A / D converter 3a is
applied to the first buffer memory 12a, and the output of the right audio A / D converter 3b is
applied to the second buffer memory 12b. The control unit 2 composed of a CPU receives a
display for which relatively high speed is not required, such as timer reservation information of
the VTR, recording, reproduction and the like of the VTR. The display screen 5 includes a general
display area 51 for displaying by the control unit 2 and a level display area 52 for displaying by
the A / D converter 3. The level display area 52 is divided into a left speech area 52a and a right
speech area 52b, and these areas 52a and 52b are a plurality of display areas V and ~ V. からな
る。 According to this embodiment, the levels of the left and right two-channel audio inputs of
stereo can be displayed at high speed independently of each other. The peak hold function can be
easily realized by providing delay characteristics at the fall of the write / invert buffer 32 (FIG. 2)
of the A / D converter 3.
FIG. 4 is a block diagram showing still another embodiment of the present invention. This
embodiment is to display the frequency spectrum of the input signal. In this embodiment, a
plurality of A / D converters 3 are provided, and correspondingly, the image buffer memory 1
includes a plurality of level display buffer memories 12. In addition, band pass filters 6 having
different center frequencies are connected to each A / D converter 3 respectively. On the other
hand, the day play screen 5 includes a plurality of level display areas 52 corresponding to the
plurality of level display buffer memories 12. The input signal is commonly input to the plurality
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of band pass filters 6, and the output from each band pass filter 6 is input to the A / D converter
3. Information corresponding to the level of each frequency component is given from each A / D
converter 3 to each level display buffer memory 12. The image signal generation circuit 4
generates an image signal corresponding to the stored contents of the level display buffer
memory 12 and causes each level display area 52 of the display screen 5 to perform level display
corresponding to each frequency component. As described above, the display of characters and
the like is controlled by the control unit 2 including the CPU, and the level display of the input
signal is performed at high speed without passing through the control unit 2 including the CPU.
The screen display device of the present invention can be used for all electronic devices that
perform display display such as a television, a radio, a computer, a measuring instrument, etc. in
the fool of the above embodiment. As described above, according to the present invention, the
information corresponding to the level of the analog input signal is directly written in the storage
area of the storage means and displayed in the display section corresponding to the storage
means. The level of the rapidly changing analog input signal is graphically displayed at high
speed without delay.
[0002]
Brief description of the drawings
[0003]
FIG. 1 is a block diagram showing an embodiment of a screen display device according to the
present invention, FIG. 2 is a diagram showing a circuit configuration of a buffer memory for
level display and an A / D converter included in the embodiment of FIG. 3 is a block diagram
showing another embodiment of the screen display device according to the present invention,
FIG. 4 is a block diagram showing still another embodiment of the screen display device
according to the present invention, and FIG. 5 is a conventional screen display device. It is a
block diagram shown.
In the figure, 1 is an image buffer memory, 2 is a control unit, 3 is an A / D converter, 4 is an
image signal generation circuit, 5 is a display screen, 11 is a general display buffer memory, 12
is a level display buffer memory, 51 indicates a general display area, and 52 indicates a level
display area. Figure 1 Figure 5
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