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? ? ? ? ? t matrix 4 f yannel for deko, ? ^ M M ? ? 3, patent applicant fyx ? fy ? ???
? ? ? 7, -2--? ? Japan Patent Office ? JP JP 51-544010 release date Sho 51. (1'976) 5, 1.3
Japanese Patent Application No. 49- / 28324-Agency Serial No. 34623 specification 1 title of the
invention z, 4! When receiving two-channel signals based on different matrix-four-channel
systems and obtaining reproduced signals conforming to each system, a variable gain amplifier
1m constructed using FETs as gain control elements is provided with the FITK. 9) A decoder for
setting a predetermined level ratio between signals according to each of the above methods by
switching control of a bias voltage to change the gain of the variable gain amplifier, and in the
same array as the FET Using two or less of F'ETs, each of these FETs generates an f-)-source
voltage or gate-drain voltage generated so as to flow a rounding one-phase current for obtaining
a desired gain of the variable gain amplifier. The voltage is applied as the FgTK bias voltage of
the variable gain amplifier, and the matrix 4-channel decoder. ?
Decoder for matrix 4 channel
Detailed Description of the Invention The present invention relates to a decoder for matrix four
channels. There are KBM (QS) system and S40,000 system which are typical as matrix 4 channel
system, and encoded signals by these two systems are usually decoded and reproduced using a
decoder that conforms to each system. Ru. However, if separate decoders are used to decode
encoded signals according to two types of systems as described above, the% reproduction
apparatus is uneconomical if it is large. Therefore, for the matrix system of these two bridges, for
example, the decoder shown in FIG. 1 can be considered as a circuit that shares most of the
circuit configuration and performs decoding reproduction adapted to each system. RN] In the
figure, the 2 channel channel code signal LTEt and RT have the same phase shift characteristics
via the ? ▒ ? ░ phase shifters J1 and 12 to the first and fll, 2 matrix circuits 13 and 14 A sum
signal LT + RT and a difference signal LT = R are respectively produced. Upper EndPage: 1
Fertilizer signal, + RF as it is, the above difference signal,-to the 1 llylf first variable gain amplifier
16 so it is then fed to the tLll E8 matrix circuit 18 and ? ((L, + R ,) + / (LT-RF)) and the ring ((L,
10R,)-/ (L, -RF)) are produced. These signals M ((L, +8. ) 10 / (L, -RF)) and VkC (t, + a,)-/ (also, =
IL,)), 0 ▒ oOsm device 11 and 1g! It is output as a front left reproduction signal LF 'and 7 and a
front right reproduction' signal RF '. -10,000 above 2 channel signal L? And R1 are the same as
described above, $ 4 and 115 q) via phase shifters 11 and 12, respectively, + 3 circuits 19 and
20 fIC supplied difference signal, -It, and sum signal, t + 11. p each made nine. The above
difference signal, -a, is that number, 11111 I,? + RFaRM (QB) Regeneration '11 KIQ conversion X
', S, and 1IJfbt) are supplied to the above-mentioned * 6 O-V circuit 21 through the second
variable gain amplifier 22'. Further, a $ 17 matrix circuit 23 is provided, which receives the twochannel signal-and B, produces a sum signal, and produces + R, and this sum signal + R. Is phaseshifted by the .phi. + Phase shifter 24 having a phase shift characteristic of 900 DEG
C. to j.sup.j) with respect to the .phi. +. Phase shifter it and is 8Q. It is supplied in
the form of Cat's variable gain amplification '1122 Kj (by + ?,).
The matrix circuit 21 of the above-mentioned ? 6 is signaled at the time of LRM (QB)
reproduction by switching of the changeover switch sl, -R, and bC + + [1? ) Are supplied
respectively to generate signals (LT-R,) + b (L, + R,) and B (L, -R,)-b (L, 10 ?, At the time of
reproduction, a signal, -R, and jb (L, t + R,) are respectively supplied, and (I, -1t,) + jb (L, + R,)) and
po (L, -R,)-1b. Create a signal of (L, + R,). These No. V! i (L, -a,) + b (L, + a,), child (t, -a,) + jb (t, + a,)
and po (L, -R,) -b (L, + R,) ) And L (L, ?R,) ? ? jb (dove)) have a phase shift characteristic of 90
? delay (1 j) with respect to the above-described ? ▒ ? ░ phase shifter 171.18, respectively.
Through the phase shifters 25 and 21F, the aM (QB), the rear left reproduction signal LB 'of 8Q
regeneration and the rear right reproduction signal R-' are output. The 11 EI and IES variable
gain amplifiers 16 and And 8. It is controlled by the bias voltage given through. The
changeover switch 8168. And S are interlocked, and when these decoders are switched to flM
(QB) regeneration, the variable gain amplifiers 1g and 22 of III and 112 have their respective
amplifications rlf and b both about 0.4. The bias voltage which gives When switched to tricks
regeneration, a bias voltage is given such that both amplification II / and b become
approximately 1. ????????????????????? By switching (?81), decoding
of RM (Qg) and SQ can be performed. That is, in the case of RM (QB) system decoding, 2-channel
engineering code signal, and R1 set the -4 channel original signal as LF, RF, LB, RB, = LF + 0.4 RF
+ j LB + J 0.4 RBR, 4F ▒ o, + XJ v If the channel reproduced signal is LF'01RF'o, LB '(1, RB'o), it is
indicated by -3as-JO, 4LB, which is obtained by reproducing it with a normal RM (QB) decoder. 1
RM (Q) 4-channel reproduced value number LP ?, RF ?, LB ?, company RB ?, LP ? = 0.7 B (L,
+0.4 B) = 072 LP ? obtained by the decoder of FIG. 8F'2O-72 (at 10-4 Lt) 2O-7 'BRF'o.
????????? 2 (L, twenty-four By) twenty-seven SLB'o. ??
??????????????????????????????? The same decoding as the
normal iLM (Qfl) decoder is performed. In the case of ninety-nine scheme decoding. 2 ? ? ? ?
? ? ? ? ? ?? ? ? ? LT ? ? ? ? ?. LT = tliP-jo: tta + o, 7anBT = IIF + jO, 7aB-0, 7LB,
and the 4-channel reproduced value obtained by reproducing it with an 8Q decoder with one
current supplied is LF'o * BF'o. LB'o + RB'o, 89494 channel reproduced value F 'obtained by the
decoder of Fig. 1, if any. ????????????????????????? EndPage: 2BP '=
By = fEF' (ILB '= ? (LT + j to 10 B,-jL,): e-ALB + O,?,-J-tLF + 0.7 ░' tar = e-jJF <tts + jO? (-T-JLt-Lt +
JRy) = for Lv-a, qayr) & B'2. ????? forward reproduction signal LP 'and aF't: C reproduction
signal LF' by the normal f3Q-P cog (a signal similar to 1 and RF'o), backward reproduction signal
LB 'and RB 'tl !, normal 8Q data; reproduction signal by-LB. And RB. And the phase is slightly
different 7 (. Signal configuration and separation are similar signals], and 5Q-P codes are
performed. In the optical decoder shown in the above 9 1) in the optical decoder ?] and aS
variable gain amplifier 16.22 set amplification W /, btRM (QS) system and QB system according
to switching of about 0.4 and about IK respectively In addition, the direction components
included in the encode signals L1 and R, K are appropriately detected according to each system,
and the large control signals E / and Ebt respectively according to the direction components are
the first and II variable gain amplifiers 16 and 22 respectively. To increase the separation
between each reproduction channel. As a specific circuit of the first and second variable gain
amplifiers 16 and 22, for example, the circuit shown in FIG. 2 shown as the first variable gain
amplifier 16 can be considered. That is, in the figure, Ql is a transistor to which a signal from the
second matrix circuit 14 is inputted to its base, and the emitter of this transistor Q is connected
as shown <FET Qt, and the internal resistance of F'ETQx is The variable gain amplifier 16 is
configured to change the gain of the amplifier consisting of transistor # Q1 by changing it.
One source of the FET Q * is set in advance by the bias power supply 210 with the variable
resistors vR1 and VB, and a large voltage is selected by the changeover switch 8.. given via t- 1.
Due to the change of the source voltage V- due to the switching of the changeover switch S, J) the
gate-north voltage Vgs of the FET Qt becomes biased, and the internal resistance changes. ! ,Up!
If the above-mentioned large control signal 'Eft is given to the gate of eFKT Qt, the above internal
resistance can be changed also by the change of this control signal E /. In the case of a
semiconductor device, it is assumed that E / = constant (the same applies to Eb) to simplify the
explanation, and a constant gate voltage Vg is applied to the gate. . By the way, the
characteristics of the internal resistance R6- at the time of conduction with respect to the sourcegate voltage Vgm of a general KFET is largely different even if it is FIT of the same kind like FETA and FIT-B shown in FIG. 9 Therefore, even if the gate voltage "-" voltage ?gs is constant and
the source voltage v8 is a pair, I! The gain of the variable gain amplifier 16 shown in FIG. 2 is not
uniform, and the pinch-off voltage Vp of each FET (for example, Vp ^, VpH shown in FIG. 118) or
the threshold voltage v? Depending on the value of I, the gain will be greatly different. If the
decoder t # I shown in FIG. 1 is formed using the circuit shown in FIG. 2 for rounding 2, the gain
of the town change interest amplifier 16 is 0.4.8Q in the case of RM (QS). In order to achieve
rounding, the variable resistors Va and vR8 of the bias power supply 2i must be adjusted
individually (and they must be adjusted individually, and the same applies to the variable gain
amplifier 22t / c in the entire decoder. The problem of having to make adjustments is nine. The
present invention has been made based on the above situation and uses FET as a gain control
element in order to perform decoding reproduction adapted to each system by sharing most
circuit configurations to different matrix systems. For a variable gain amplifier with uniform KWI
configuration in which the gain is switched according to the above system, it is possible to easily
set the gain according to each system, and to provide a decoder for fe matrix 4 channels The
purpose is to do things. EndPage: An embodiment of the present invention will be described with
reference to the WJ plane of 3 or less. As described above, the round naked KFIT #: E gate-source
voltage Vgs vs. internal resistance Ran characteristics tend to be largely parallel in general, but
the FETt formed in the same-double lay! The above-mentioned characteristics are very good (all
in all. As shown in the case of using a P-channel enhancement mode ItFET in FIG. 9B, when the rgate voltage Vg is a constant value, a source current of Il flows to make the source resistance RIIt
constant, IPETQst?. When operated as a source follower, vD11 (source-drain voltage) / Is (no
current) of the FET Q of the kernel is substantially constant, and if the same kind of FET t-is used,
a plurality of similar circuits are configured. Also, the VDs / II has a substantially constant value
because the influence of the pin-off lami pressure Vp of each FET due to the parang dFK is small.
That is, in the case of such connection, when the source current Is changes at the f?) voltage Vg
= ?foot, the r?tonse current EEVgs changes according to the change of the kernel, and the
internal resistance Ron of the PET is the source current The source-drain contact pressure V ? is
substantially determined by Is alone, and there is a characteristic that the source / drain pressure
V ? becomes a predetermined value according to the value of the source current Is. This is
because the PKTO) f'-tonse voltage Vgs characteristic (related to vp or V @) largely changes due
to the impurity diffusion process etc. which is learned in the semiconductor manufacturing
process as described above. Source current in the source follower which is not constant ? s:
source-drain ? EEV 4? The eight characteristics are a certainty, and are determined by the FIT
putter in semiconductor manufacture. If a circuit as shown in the figure fIN4 is used as a circuit
for reference and the voltage Vgavt between the gate and the source of the FET obtained from
this circuit is applied to the P-transistor of another FET in the same array as the EFET, The
internal resistances Ran of these FITs will be set to almost equal values. That is, the source
current I of the reference FET has a predetermined value such that a part of the nine FETs is used
as a reference and the other is used for gain control of the variable gain amplifier. Gate voltage at
9 o'clock,-voltage between V source 1 and FIT (7) for the above-mentioned advantageous control.
-)-When given to the source function, the gain of the variable gain amplifier can be determined in
the case of the variable gain amplifier to be nine gains. Therefore, the variable gain amplification
section in the decoder for matrix 4 channel according to the present invention is #I configured as
shown for example by the first svAK. In the figure, reference numerals 16 and 22 respectively
denote a gain variation amplifier configured in substantially the same manner as in FIG. 2 using a
transition 161, a FIT 16J for gain control, a transistor 2721 and a FET zJzf for gain control.
Further, 271 and 212 use FETi formed in the same array as both FETs 16j and Jjj above, apply a
gate voltage of Eo from the control circuit 2rs to each of the nine gates, and predetermined via
resistors R3 and R. It is an FgT for reference corresponding to the RM (Q8) system and the SQ
system, each of which is configured to operate as a source door by supplying a source current),
and switching these reference FETs 2rl and 2r2Tri changeover switches S and S. The respective
gate-source voltages are in this case via the control circuit 211 'and the gain control PE 7162
described above.
It is made to give to 222. That is, FET I6j for gain control,! ,? The internal resistance of Z has a
good value according to the source current of the reference FETs 271 and 222 determined by
the resistors R1 and R3. Therefore, with the above configuration, each variable gain can be
obtained by setting resistances R1 and R3 in advance according to each method so that a source
current of a specific value can be supplied to FITs 271 and 212 for reference. The internal
resistance of the gain control FET 162.222 of the amplifier 16.22 can be simultaneously set to a
predetermined value, and the gain of the variable gain amplifier 16.22 can be set according to
each system. From the pre-control circuit 213, P-) K giving voltage E / and UEbtFET for gain
control FETs 162 and 222: pn. F-) End page: 4 if not properly changed according to the voltage E,
if appropriately changed in the predetermined range, the town, the smart gain amplifier 1-6 and
220 gain tt are moved accordingly It is also possible to improve the separation between the
reproduction channels. In this way, the resistances R1 and Bt respectively determined for the q7
array> x FIT j rJ and 2 rs band charges respectively corresponding to the respective systems are
set in advance by simultaneously setting the gains of the variable gain amplifiers 16 and 2-1 The
setting can be made carefully, and the adjustment I1 can be performed. Of course, the present
invention is limited to the embodiment described above and shown in the drawings, and various
modifications can be made within the scope of the invention without changing the gist of the
invention. For example, in the above example, i'C uses i as reference FITJ 71 and 212 as a source
follower, but when the source address is modified, for example, ? 6 (a) (P-channel FET jFI ', JFj'
is Jllvh) Alternatively, Fig. (B) (N-channel Fg'rZrI '. When used as a 212 'holder) as a circuit as
shown. -Even if it does, it can be controlled as above. The connection S of one substrate terminal
in the case of O may be the same as that shown in FIG. 5 or other connection. Furthermore, in
each of the above-mentioned practical examples, gain control of r-to-source voltage of reference
Fg is performed. Even if it is given as the FET K bias charge i for the 'gate-bill 42', the same effect
can be obtained as described above. According to the present invention described above,
according to the present invention, the circuit configuration of large S minutes is shared to the Qtype system, and nine-decode reproduction is performed to be compatible with each one system,
FgTt1iIl is a gain control element and large control It is also possible to switch the gain of the
element amplifier according to the above-mentioned system rc @ and also at least two other FETs
& each of each system formed in the same array as the 27E as the gain control element. For
reference purpose i, by making each of these FITK flow a predetermined current, the P-) source
voltage ytnFiy-to-to-train voltage is used as the bias voltage of FIT as the gain control element.
Thus, it is possible to provide a decoder for matrix number channel in which setting of gain can
be easily performed according to each system.
4. Brief description of the drawings. FIG. 1 is a plotter showing the configuration of the
switchable RM system and 8Q system = conider, FIG. 2 is an rgTt 11111 element used for the
decoder of the video decoder 9 variable gain amplifier and its FIG. 12 is a circuit diagram
showing an example of a vias power supply. FIG. 118 is a diagram showing the variance dPe of
the characteristics of internal resistance with respect to the gate-to-tooth voltage Vg + a of the
FET. FIG. 1114 is a diagram for explaining the source follower circuit of the FET. FIG. 6 is a
circuit diagram showing an embodiment of the present invention, and FIGS. 6 (a) and 6 (b) are
main part circuit diagrams showing another embodiment of the present invention. 16.22 иии
Variable gain amplifier, 161.221 и и и Transistor% 162, 222 и и и FET for gain control, 2fl, 2jll ',
211', '12 ░ 21 J ', JFJ'-и и и for reference FIST, 2F! ... control circuit. EndPage: 5 Oki 2 @ -2F30,
Oki 4 @ Oki 5 [l-Oki 6 [I-(a) (b)-EndPage: 65, List of attached documents 6. Inventors, patent
applicants or agents other than those mentioned above JP-A 51-544 "01 (7) EndPage: ?
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